Two or more semiconductor packages are stacked with an intervening element that is positioned between within an area surrounded by conductive bumps of a bottom surface of the overlying package. Different shapes of the intervening element are used depending upon how many sides of the bottom surface have conductive bumps. In one form the intervening element extends laterally from the stack and is bent downward to contact or extend through an underlying substrate. Contact to the intervening element at the backside of the substrate may be made. In another form the intervening element is bent upward for enhancing thermal properties. The intervening element is adhesive to prevent non-destructive removal of the packages thereby adding increased security for information contained within the packages. Selective electrical shielding between packages is also provided.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A stacked semiconductor package assembly comprising: a first semiconductor package comprising a first surface having a first plurality of conductive bumps attached thereto for making electrical connection to the first semiconductor package, and comprising an opposite and nonplanar second surface comprising a mold cap and a plurality of adjoining electrical contacts; a second semiconductor package overlying the first semiconductor package comprising a first surface and an opposite second surface, the second surface comprising a second plurality of conductive bumps positioned outside of a central portion of the second surface and in contact with the plurality of adjoining electrical contacts of the first semiconductor package, the second semiconductor package making direct electrical contact to the first semiconductor package via the second plurality of conductive bumps; an intervening element positioned in direct contact with and between the first semiconductor package and the second semiconductor package, the intervening element being sufficiently tacky to adhere to each of the first semiconductor package and the second semiconductor package and provide rigidity to adjoining surfaces of the first semiconductor package and the second semiconductor package in contact with the intervening element, the intervening element being surface conformal to the first semiconductor package and the second semiconductor package, the intervening element extending laterally outside a perimeter of at least one of the first semiconductor package and the second semiconductor package and bending a predetermined amount; and an underlying substrate having a plurality of contacts, each of the plurality of contacts of the underlying substrate being in contact with at least one of the first plurality of conductive bumps of the first semiconductor package.
2. The stacked semiconductor package assembly of claim 1 wherein the intervening element is a thermally activated material.
3. The stacked semiconductor package assembly of claim 1 wherein the second semiconductor package is a data storage integrated circuit for storing secure data.
4. The stacked semiconductor package assembly of claim 1 wherein the intervening element extends laterally outside from a perimeter of the first semiconductor package and the second semiconductor package.
5. The stacked semiconductor package assembly of claim 4 wherein the intervening element extends laterally outside from a perimeter of the first semiconductor package and the second semiconductor package and is angled in a direction away from the underlying substrate.
6. The stacked semiconductor package assembly of claim 4 wherein the intervening element extends laterally outside from a perimeter of the first semiconductor package and the second semiconductor package and is angled toward the underlying substrate to make electrical contact thereto.
7. The stacked semiconductor package assembly of claim 6 wherein the intervening element is connected to at least one of an electrically conductive or an insulating terminal when electrical contact to the underlying substrate is made.
8. The stacked semiconductor package assembly of claim 4 wherein the intervening element extends laterally outside from a perimeter of the first semiconductor package and the second semiconductor package and is angled toward and through the underlying substrate for making at least one of electrical or physical contact thereto from a back side of the underlying substrate.
9. The stacked semiconductor package assembly of claim 1 wherein the second plurality of conductive bumps of the second semiconductor package that are positioned outside of a central portion of the second surface are positioned along only two opposing sides of the second surface and the intervening element extends laterally from the stacked semiconductor package assembly from an adjacent two opposing sides of the second surface.
10. The stacked semiconductor package assembly of claim 1 wherein the intervening element extends from above the mold cap to physically contact the underlying substrate for noise isolation and thermal enhancement of the stacked semiconductor package assembly.
11. A stacked semiconductor package assembly comprising: a first semiconductor package comprising a first surface having a first plurality of contacts for making electrical connection to the first semiconductor package, and comprising an opposite second surface comprising a second plurality of contacts; a second semiconductor package overlying the first semiconductor package comprising a first surface and an opposite second surface, the second surface comprising a third plurality of contacts positioned thereon and respectively in contact with the second plurality of contacts of the first semiconductor package, the second semiconductor package making direct electrical contact to the first semiconductor package; an intervening element positioned in direct contact with and between a portion of the first semiconductor package and the second semiconductor package, the intervening element being sufficiently tacky to adhere to each of the first semiconductor package and the second semiconductor package and provide rigidity to adjoining surfaces of the first semiconductor package and the second semiconductor package in contact with the intervening element, the intervening element being surface conformal to the first semiconductor package and the second semiconductor package and comprising a portion that extends laterally from a periphery of the stacked semiconductor package assembly and bends at a predetermined angle; and an underlying substrate having a fourth plurality of contacts, at least one of the fourth plurality of contacts of the underlying substrate being in contact with at least one of the first plurality of contacts of the first semiconductor package.
12. The stacked semiconductor package assembly of claim 11 wherein the intervening element is angled in a direction away from the underlying substrate.
13. The stacked semiconductor package assembly of claim 11 wherein the intervening element extends laterally outside from a perimeter of the first semiconductor package and the second semiconductor package and is angled toward the underlying substrate to make electrical contact thereto.
14. The stacked semiconductor package assembly of claim 13 wherein the intervening element is connected to at least one of an electrically conductive or an insulating terminal when electrical contact to the underlying substrate is made.
15. A stacked semiconductor package assembly comprising: a first semiconductor package comprising a first surface having a first plurality of conductive bumps attached thereto for making electrical connection to the first semiconductor package, and comprising an opposite and nonplanar second surface comprising a mold cap and an adjoining plurality of electrical contacts; a second semiconductor package overlying the first semiconductor package comprising a first surface and an opposite second surface, the second surface comprising a second plurality of conductive bumps positioned outside of a central portion of the second surface and in electrical contact with the plurality of adjoining electrical contacts of the first semiconductor package, the second semiconductor package making electrical contact to the first semiconductor package via the second plurality of conductive bumps; a thermally conductive adhesive layer positioned in at least a central region of the stacked semiconductor package assembly and in direct contact with and between the first semiconductor package and the second semiconductor package and overlying the mold cap of the first semiconductor package, a portion of the thermally conductive adhesive layer extending from the central region and bending downward to physically separate at least one of the plurality of electrical contacts and one of the second plurality of conductive bumps; and an underlying substrate having a plurality of contacts, each of the plurality of contacts of the underlying substrate being in contact with at least one of the first plurality of conductive bumps of the first semiconductor package.
16. The stacked semiconductor package assembly of claim 15 wherein the at least one of the plurality of electrical contacts and the one of the second plurality of conductive bumps are connected to at least one of an electrically conductive or an insulating terminal to further enhance at least one of electrical shielding or heat dissipation between the first semiconductor package and the second semiconductor package.
17. The stacked semiconductor package assembly of claim 15 wherein the thermally conductive adhesive layer comprises a film of thermally activated flexible material.
18. The stacked semiconductor package assembly of claim 15 wherein the second semiconductor package is a data storage integrated circuit for storing secure data.
19. The stacked semiconductor package assembly of claim 15 wherein the portion of the thermally conductive adhesive layer that extends from the central region extends laterally between multiple ones of the plurality of electrical contacts and the second plurality of conductive bumps toward at least two sides of the stacked semiconductor package assembly.
20. The stacked semiconductor package assembly of claim 15 wherein a second portion of the thermally conductive adhesive layer extends laterally beyond an outer edge of the stacked semiconductor package assembly.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 18, 2005
March 27, 2007
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