A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a switch circuit for selectively coupling a respective first signal input/output node thereof to a respective second signal input/output node thereof, the switch circuit being responsive to at least one control signal having a state corresponding to a voltage level no larger than a power supply voltage when the power supply voltage is a first value, and responsive to at least one control signal having a state corresponding to a voltage level that is larger than the power supply voltage when the power supply voltage is a second value, the second value being lower than the first value.
2. The apparatus, as recited in claim 1 , wherein respective voltage levels of the first and second signal input/output nodes remain no larger than the power supply voltage for both first and second values thereof.
3. The apparatus, as recited in claim 1 , wherein the switch circuit has a static characteristic that is improved by use of the control signal having the state corresponding to the voltage level larger than the power supply voltage when the apparatus is operated at the second value of the power supply voltage.
4. The apparatus, as recited in claim 3 , wherein the static characteristic comprises a transfer function of the switch circuit, which is continuous over a larger range of input voltages by use of the control signal having the state corresponding to the voltage level larger than the power supply voltage.
5. The apparatus, as recited in claim 1 , further comprising: a control circuit for generating a group of one or more control signals, at least one of the group having a state corresponding to a voltage level no larger than the power supply voltage when the power supply voltage is the first value, and at least one of the group having a state corresponding to a voltage level which is larger than the power supply voltage when the power supply voltage is the second value.
6. The apparatus, as recited in claim 5 , wherein the control circuit is configured for generating a pair of non-overlapping, complementary clock signals, each having a high voltage level no greater than the power supply voltage when the power supply voltage is the first value, and each having a high level above the power supply voltage when the power supply voltage is the second value.
7. The apparatus, as recited in claim 5 , wherein the control circuit is configured for generating a pair of non-overlapping complementary clock signals each having a high voltage level no greater than the power supply voltage when the power supply voltage is the first as well as the second value, and configured for generating at least another clock signal having a high level above the power supply voltage when the power supply voltage is the second value.
8. The apparatus as recited in claim 5 , wherein the control circuit comprises: a first input node and a second input node responsive to at least respective ones of a first pair of non-overlapping clock signals having a first voltage level in respective first phases and a second voltage level in respective second phases; a first node and a second node configured to provide a second pair of non-overlapping clock signals having the second voltage level in respective first phases and a third voltage level in respective second phases; a first output stage and a second output stage responsive to at least respective ones of the first and second input nodes and responsive to at least respective ones of the first and second nodes and configured to provide a third pair of clock signals having the first voltage level in respective first phases and the third voltage level in respective second phases; wherein the first voltage level is the ground voltage, the second voltage level is the power supply voltage, and the third voltage level has a magnitude larger than the power supply voltage; and wherein the group of one or more control signals comprises at least one of the third pair of clock signals.
9. The apparatus, as recited in claim 8 , wherein individual ones of the pair of output stages comprise: a first inverter circuit responsive to at least the power supply voltage, the ground voltage, and a respective one of the first and second input nodes; and a second inverter circuit responsive to at least a respective one of the first and second nodes, a ground voltage, and an output of the first inverter circuit.
10. The apparatus, as recited in claim 8 , wherein the apparatus further comprises: a clock generation circuit coupled to the first and second input nodes of the control circuit and configured to provide the first pair of non-overlapping clock signals.
11. The apparatus, as recited in claim 1 , further comprising: a circuit portion comprising at least transistors of a first transistor type of a first conductivity type, the first transistor type having a first threshold voltage of an absolute value less than the power supply voltage; and wherein the switch circuit comprises at least a transistor coupled to the first and second signal input/output nodes, the transistor being of a second transistor type, also of the first conductivity type, the second transistor type having a second threshold voltage higher in magnitude than the first threshold voltage.
12. The apparatus, as recited in claim 11 , wherein the transistor of the second transistor type has an oxide thickness greater than an oxide thickness of the transistors of the first transistor type.
13. The apparatus, as recited in claim 11 , wherein the transistor of the second transistor type has a lower leakage current than the transistors of the first transistor type under equivalent bias conditions.
14. The apparatus, as recited in claim 11 , wherein the second threshold voltage has an absolute value of at least the magnitude of the second value of the power supply voltage.
15. The apparatus as recited in claim 11 , wherein the switch circuit further comprises at least a second transistor coupled to the first and second signal input/output nodes and having the second conductivity type and responsive to at least a complement of the selected one of the control signals.
16. The apparatus as recited in claim 1 , wherein the switch circuit forms a portion of a switched capacitor circuit.
17. The apparatus as recited in claim 1 , embodied in computer readable descriptive form suitable for use in design, test, or fabrication of an integrated circuit.
18. A method comprising: coupling a respective first signal input/output node to a respective second signal input/output node according to at least a selected one of at least a first control signal and a second control signal; wherein the first control signal has a state corresponding to a voltage level no larger than a power supply voltage when the power supply voltage is a first value; wherein the second control signal has a state corresponding to a voltage level that is larger than the power supply voltage when the power supply voltage is a second value; and wherein the second value is lower than the first value.
19. The method, as recited in claim 18 , further comprising: generating the second control signal when the power supply voltage is the second value.
20. The method, as recited in claim 19 , further comprising: generating a DC voltage level larger than the power supply voltage for generating the second control signal when the power supply voltage is the second value.
21. The method, as recited in claim 20 , wherein a clock driver circuit generates the control signal and the voltage level larger than the power supply voltage.
22. The method, as recited in claim 19 , wherein the generating the control signal comprises: charging a first node and a second node to a first voltage level no larger than the power supply voltage; boosting the voltage on the first node and the second node from the first voltage level to a second voltage level larger than the power supply voltage, the voltage on the first node being boosted out of phase with the boosting of the voltage on the second node; driving a first output node and a second output node to the second voltage level by the first node and the second node, the second output node being driven out of phase with the first output node; and discharging the first and second output nodes to ground, the second output node being discharged out of phase with the first output node.
23. The method, as recited in claim 22 , wherein the generating the control signal further comprises: generating a pair of non-overlapping clock signals to at least charge and boost the voltages on the first and second nodes.
24. The method, as recited in claim 18 , further comprising: implementing portions of a circuit using at least transistors of a first transistor type of a first conductivity type, the first transistor type having a first threshold voltage of an absolute value less than the power supply voltage; and wherein the coupling comprises providing at least a transistor coupled to the first and second signal input/output nodes, the transistor being of a second transistor type, also of the first conductivity type, the second transistor type having a second threshold voltage higher in magnitude than the first threshold voltage and responsive to at least the control signal having a state corresponding to a voltage level larger than the power supply voltage.
25. The method, as recited in claim 24 , wherein the transistor of the second transistor type has an oxide thickness greater than an oxide thickness of the transistors of the first transistor type.
26. The method, as recited in claim 24 , wherein the transistor of the second transistor type has a lower leakage current than the transistors of the first transistor type.
27. The method, as recited in claim 24 , wherein the second threshold voltage has an absolute value of at least the magnitude of the second value of the power supply voltage.
28. The method as recited in claim 24 , wherein the coupling further comprises providing at least a second transistor coupled to the first and second signal input/output nodes and having the second conductivity type and responsive to at least a complement of the selected one of the control signals.
29. The method, as recited in claim 18 , further comprising: holding a charge proportional to a signal transferred between the first signal input/output node of the switch and a second signal input/output node of the switch on a capacitive node of a sample of hold circuit.
30. An apparatus comprising: means for generating at least a first control signal having a state corresponding to a voltage level no larger than a power supply voltage when the power supply voltage is a first value; means for generating at least a second control signal having a state corresponding to a voltage level that is larger than the power supply voltage when the power supply voltage is a second value, the second value being lower than the first value; means for selecting one of the first control signal and the second control signal according to at least a value of the power supply voltage; and means for coupling a first signal input/output node to a second signal input/output node according to at least the selected one of the first control signal and the second control signal.
31. The apparatus, as recited in claim 30 , wherein the means for generating the second control signal comprises: means for generating the voltage level that is larger than the power supply voltage.
32. The apparatus, as recited in claim 30 , further comprising: a circuit means comprising at least transistors of a first transistor type of a first conductivity type, the first transistor type having a first threshold voltage of an absolute value less than the power supply voltage; and wherein the coupling means comprises at least a transistor coupled to the first and second signal input/output nodes, the transistor being of a second transistor type, also of the first conductivity type, the second transistor type having a second threshold voltage higher in magnitude than the first threshold voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 30, 2005
April 3, 2007
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.