An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. Current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. Dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An antifuse cell comprising: an antifuse comprising a capacitor, the capacitor having a first end and a second end, the first end of the capacitor being configured to receive a programming voltage to burn an electrically conductive path through the capacitor when the antifuse cell is selected; a select transistor configured to allow selection of the antifuse cell among a plurality of antifuse cells; a blocking transistor configured to limit an amount of voltage applied to the select transistor; and a dynamic current limiting resistor in series with the capacitor to limit dynamic current flowing to ground by way of a substrate of the antifuse during programming of the antifuse cell.
2. The antifuse cell of claim 1 wherein the antifuse further comprises a diode having a cathode end coupled to the second end of the capacitor and an anode end coupled to ground.
3. The antifuse cell of claim 2 wherein the second end of the of the capacitor is coupled to a drain of the blocking transistor, a drain of the select transistor is coupled to a source of the blocking transistor, and a source of the select transistor allows for sensing of a state of the antifuse.
4. The antifuse cell of claim 1 wherein the capacitor comprises: a polysilicon gate serving as a top plate of the capacitor; an n-well serving as a bottom plate of the capacitor; and a gate oxide between the polysilicon gate and the n-well, the gate oxide serving as a dielectric of the capacitor.
5. The antifuse cell of claim 4 further comprising: a first n+ region; and a second n+ region, wherein the n-well lies between the first and second n+ regions.
6. The antifuse cell of claim 5 wherein the first and second n+ regions are shorted together.
7. The antifuse cell of claim 4 wherein the polysilicon gate is the first end of the capacitor.
8. The antifuse cell of claim 1 wherein the capacitor is coupled to ground by way of a p-type substrate where the capacitor is formed.
9. The antifuse cell of claim 1 wherein the electrically conductive path has a resistance of about 5 kΩ.
10. The antifuse cell of claim 1 wherein the capacitor is formed in a p-type substrate.
11. The antifuse cell of claim 1 wherein the blocking transistor and the select transistor comprise MOS transistors.
12. The antifuse cell of claim 1 where the blocking transistor and the select transistor comprises NMOS transistors with a common n+ region.
13. A method of programming an antifuse cell of an integrated circuit, the method comprising: selecting an antifuse cell in an array of antifuse cells, the antifuse cell comprising an antifuse having a capacitor; applying a programming voltage at a first node of the antifuse cell to program the antifuse cell by burning an electrically conductive path through an oxide of the capacitor; and using a dynamic current limiting resistor to limit a dynamic current flowing to ground through a substrate of the antifuse during programming, the dynamic current limiting resistor being in series with a programming current flowing through the oxide.
14. The method of claim 13 further comprising: preventing the programming voltage from being directly applied to a transistor used to select the antifuse cell.
15. The method of claim 13 wherein the dynamic current limiting resistor is located in series between the first node and a top plate of the capacitor.
16. The method of claim 13 wherein the capacitor comprises a gate serving as a top plate of the capacitor, an n-well serving as a bottom plate of the capacitor, and the oxide serving as a dielectric of the capacitor.
17. An antifuse cell programmable using the method of claim 13 .
18. An antifuse cell comprising: capacitor means for creating a short through a gate oxide in response to a signal to program the antifuse cell, the capacitor means comprising a capacitor; selection means for selecting the antifuse cell for programming or reading; blocking means for limiting an amount of voltage applied to the selection means; and current limiting means for limiting dynamic current flowing to ground by way of a substrate of the antifuse cell during programming of the antifuse cell.
19. The antifuse cell of claim 18 wherein the capacitor means comprises two active n+ regions separated by an n-well.
20. The antifuse cell of claim 18 wherein the selection means and the blocking means comprise NMOS transistors.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 29, 2005
April 17, 2007
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.