The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating film spacer at a region where the plug is not formed to lower the aspect ratio between the metal lines, in a process of burying an insulating material between the metal lines to electrically insulate them. Therefore, the present invention can easily bury the insulating material even between the metal lines having a narrow gap without voids.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming an interlayer dielectric film in a semiconductor device, the method comprising: forming conductive layer pattern on a semiconductor substrate including a junction region and an isolation region; forming insulating film spacers on sidewalls of said conductive layer pattern to expose the junction region; burying a conductive material between said insulating film spacers; removing said conductive material and said insulating film spacers in the isolation region; and forming an interlayer dielectric film on an entire surface of the semiconductor device so that the interlayer dielectric film is buried between the conductive layer pattern in the isolation region.
2. The method of according to claim 1 , wherein said conductive layer pattern includes a word line or a bit line.
3. A method of forming an interlayer dielectric film in a semiconductor device, the method comprising: forming conductive layer patterns and an insulating film spacers on sidewalls of said conductive layer patterns on a semiconductor substrate to expose a first contact plug; forming a conductive material on the entire surface to bury the conductive material between said insulating film spacers; removing said conductive material and the insulating film spacers at a removal region such that said conductive material remains on the first contact plug to form a second contact plug and the insulating film spacers only remain at both sides of the second contact plug; and burying an interlayer dielectric film between said conductive layer patterns at said removal region.
4. The method according to claim 3 , wherein said conductive layer pattern includes a bit line.
5. A method of forming an interlayer dielectric film in a semiconductor device, the method comprising: forming first conductive layer patterns on a semiconductor substrate including a junction region and an isolation region; forming first spacers on sidewalls of the first conductive layer patterns; removing the first spacers on the isolation region; forming a first interlayer dielectric film on the entire surface; forming a first contact hole by patterning the first interlayer dielectric film to expose the junction region; forming a first contact plug by burying a first conductive material in the first contact hole; forming second conductive layer patterns on the entire surface including the first contact plug; forming second spacers on sidewalls of the second conductive layer patterns; forming a second conductive material on the entire surface to bury the second conductive material between the second conductive patterns; forming a second contact plug by remaining the second conductive material on the first contact plug and removing the second conductive material and the second spacers on the first interlayer dielectric film, wherein the second spacers remains at both side of the second contact plug; and forming a second interlayer dielectric film on the entire surface;
6. The method according to claim 5 , wherein the first conductive layer patterns comprises a word line.
7. The method according to claim 5 , wherein the second conductive layer patterns comprises a bit line.
8. The method according to claim 5 , wherein the second conductive material includes a polysilicon.
9. The method according to claim 5 , wherein the second conductive layer patterns further includes nitride film.
10. The method according to claim 5 , the method further comprising: performing a first planarization process to remove the second conductive material on the second conductive patterns after forming the second conductive material.
11. The method according to claim 5 , the method further comprising: performing a second planarization process after forming the second interlayer dielectric film on the entire surface.
12. The method according to claim 5 , wherein the first spacers is remained at both side of the first contact plug.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 29, 2004
May 1, 2007
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