A system and method of providing a voltage to a non-volatile memory. The system includes an output pin to provide an output voltage to a non-volatile memory and includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin prior to a read operation on the non-volatile memory. The voltage mode module applies a second voltage at a second of the plurality of voltage levels at the output pin in response to a read operation that returns a failure condition.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: an output pin to provide an output voltage to a non-volatile memory; a memory to store a table including a plurality of operating voltage levels; and a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin prior to a first read operation on the non-volatile memory, wherein the voltage mode module applies a second voltage at a second of the plurality of voltage levels at the output pin in response to the first read operation returning a failure condition.
2. The integrated circuit of claim 1 , further comprising: an input pin; a direct current to direct current converter to convert a voltage received at the input pin to an output voltage, wherein a voltage at the output pin is based on the output voltage.
3. The integrated circuit of claim 2 , further comprising: control logic responsive to the voltage mode module to control a conversion mode of the direct current to direct current converter.
4. The integrated circuit of claim 1 , wherein the voltage mode module applies a third voltage at a third of the plurality of voltage levels at the output pin in response to a second read operation on the non-volatile memory returning a failure condition.
5. The integrated circuit of claim 2 , wherein the voltage received at the input pin is applied via a universal serial bus (USB) connection.
6. The integrated circuit of claim 1 , wherein the memory includes a table of non-volatile memory devices.
7. The integrated circuit of claim 6 , wherein the table of non-volatile memory devices includes a plurality of entries, each entry in the plurality of entries associated with an expected result of the read operation.
8. The integrated circuit of claim 1 , wherein the integrated circuit does not include a dedicated non-volatile memory voltage detection pin.
9. A method, comprising: providing a predetermined voltage at a first voltage level to a non-volatile memory prior to performing a read operation; performing a first read operation on the non-volatile memory; comparing a result of the first read operation to an expected result; and providing a voltage at a second voltage level to the non-volatile memory.
10. The method of claim 9 , further comprising: switching a conversion mode of a direct current to direct current converter after comparing the received data.
11. The method of claim 9 , wherein the result of the first read operation is compared to a table.
12. The method of claim 9 , wherein the first voltage level is about 1.8 volts and the second voltage level is about 3.3 volts.
13. The method of claim 9 , wherein the non-volatile memory is a NAND flash memory.
14. The method of claim 9 , wherein the first voltage level is based on a battery voltage level.
15. The method of claim 9 , further comprising performing a second read operation on the non-volatile memory; determining a memory instruction set based on the result of the second read operation.
16. The method of claim 15 , wherein the result of the second read operation is device identification data.
17. The method of claim 9 , wherein the device identification data is associated with a manufacturer of the non-volatile memory.
18. A method of receiving a voltage at a non-volatile memory device, comprising receiving a first voltage from at a power input pin prior to receiving a read operation instruction; receiving a first read operation instruction; providing a result of the first read operation instruction indicating a failure condition; and receiving a second voltage at the power input pin, the second voltage different from the first voltage.
19. The method of claim 18 , further comprising: receiving a second read operation instruction; providing device identification information.
20. The method of claim 19 , further comprising: receiving a third read operation instruction; providing further device identification information.
21. The method of claim 18 , wherein the first voltage is about 3.3 volts and the second voltage is about 1.8 volts.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 23, 2005
May 1, 2007
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.