The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a stacked semiconductor device package. The methods and apparatus include providing a first semiconductor device with an adhesive flow control dam located on an upper surface thereof. The dam is positioned between electrical contacts and a substrate attach site on the upper surface of the first semiconductor device. The dam is rendered of a sufficient height and shape to block applied adhesive from flowing over the electrical contacts of the first semiconductor device when a second substrate is mounted onto the upper surface of the first semiconductor device. The semiconductor device package may be encapsulated with the dam in place or with the dam removed. The adhesive flow control dam thus protects the electrical contacts of the first semiconductor device from contamination by excess adhesive, which can result in unusable electrical contacts.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A plurality of semiconductor die for an assembly comprising: a first semiconductor die of a plurality of semiconductor die in a wafer, the first semiconductor die having an upper surface, the upper surface comprising a plurality of electrical contacts and at least one region for mounting a second semiconductor die; at least one adhesive flow control dam formed on the first semiconductor die when a plurality of semiconductor die are in a wafer form prior to the singulation of the plurality of semiconductor die from the wafer for preventing flow of an adhesive applied in the at least one region of the first semiconductor die onto the plurality of electrical contacts during the mounting of a second semiconductor die, the at least one adhesive flow control dam positioned between the at least one region for mounting a second semiconductor die and each electrical contact of the plurality of electrical contacts; and a second semiconductor die, the second semiconductor die adhesively mounted onto the at least one region for the mounting a second semiconductor die of the first semiconductor die.
2. The plurality of semiconductor die of claim 1 , further comprising an encapsulant surrounding at least a portion of surface area of the first semiconductor die and the second semiconductor die.
3. The plurality of semiconductor die of claim 1 , further comprising a carrier substrate, the first semiconductor die being disposed on the carrier substrate.
4. The plurality of semiconductor die of claim 1 , further comprising a mounting adhesive disposed on at least a portion of a region of the upper surface of the first semiconductor die, at least a portion of the mounting adhesive disposed between the at least one adhesive flow control dam and the second semiconductor die.
5. The plurality of semiconductor die of claim 4 , wherein the mounting adhesive is configured to be thermally conductive having an exposed surface area being heat dissipative.
6. The plurality of semiconductor die of claim 5 , wherein the mounting adhesive comprises an Ag-filled polymer.
7. The plurality of semiconductor die of claim 4 , wherein the mounting adhesive is configured to have a coefficient of thermal expansion selected from a group consisting of a coefficient of thermal expansion of the first semiconductor die, a coefficient of thermal expansion of the second semiconductor die, and an average of the coefficients of thermal expansion of the first semiconductor die and the second semiconductor die.
8. The plurality of semiconductor die of claim 1 , wherein the at least one adhesive flow control dam comprises at least one decoupling capacitor coupon.
9. The plurality of semiconductor die of claim 8 , wherein an adhesive used to mount the second semiconductor die includes an electrically insulating adhesive.
10. The plurality of semiconductor die of claim 1 , wherein the at least one adhesive flow control dam comprises a material selected from a group consisting of polyimides, polyamides, and epoxies.
11. The plurality of semiconductor die of claim 1 , wherein the at least one adhesive flow control dam includes a flow control dam more viscous than an adhesive used to adhesively mount the second semiconductor die.
12. The plurality of semiconductor die of claim 1 , wherein the first semiconductor die is larger than the second semiconductor die.
13. The plurality of semiconductor die of claim 1 , wherein the first semiconductor die is substantially the same size as the second semiconductor die.
14. The plurality of semiconductor die of claim 1 , wherein the first semiconductor die comprises an integrated circuit semiconductor die.
15. The plurality of semiconductor die of claim 1 , wherein the second semiconductor die comprises an integrated circuit semiconductor die.
16. The plurality of semiconductor die of claim 14 , wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.
17. The plurality of semiconductor die of claim 15 , wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.
18. The plurality of semiconductor die of claim 1 , wherein the first semiconductor die comprises an interposer.
19. The plurality of semiconductor die of claim 1 , wherein the second semiconductor die is mounted in an offset fashion relative to the first semiconductor die.
20. The plurality of semiconductor die of claim 1 , wherein at least a portion of the second semiconductor die is in contact with the at least one adhesive flow control dam.
21. The plurality of semiconductor die of claim 20 , wherein the at least one adhesive flow control dam is configured to deform upon the contact with the second semiconductor die.
22. The plurality of semiconductor die of claim 1 , wherein the at least one adhesive flow control dam extends substantially across an entire width of the first semiconductor die.
23. The plurality of semiconductor die of claim 1 , further comprising at least one wire bond extending from at least one electrical contact of the plurality of electrical contacts.
24. The plurality of semiconductor die of claim 23 , wherein the at least one adhesive flow control dam is further configured to prevent solder flow onto at least a portion of the second semiconductor die or an extension thereof during wire bonding of at least one electrical contact of the plurality of electrical contacts.
25. A stacked semiconductor die assembly comprising: a first semiconductor die of a plurality of semiconductor die in a wafer, the first semiconductor die having an upper surface including a plurality of electrical contacts, at least one region for mounting a second semiconductor die, and at least one adhesive flow control dam formed on the first semiconductor die when a plurality of semiconductor die are in a wafer form prior to the singulation of the plurality of semiconductor die from the wafer for preventing flow of an adhesive from the at least one region onto the plurality of electrical contacts during the mounting of a second semiconductor die on the first semiconductor die, the at least one adhesive flow control dam positioned between the at least one region for mounting a second semiconductor die and each electrical contact of the plurality of electrical contacts; and a second semiconductor die, the second semiconductor die adhesively mounted onto the at least one region for the mounting a second semiconductor die of the first semiconductor die.
26. The stacked semiconductor die assembly of claim 25 , further comprising an encapsulant surrounding at least a portion of a surface area of the first semiconductor die and the second semiconductor die.
27. The stacked semiconductor die assembly of claim 25 , further comprising a carrier substrate, the first semiconductor die being disposed on the carrier substrate.
28. The stacked semiconductor die assembly of claim 25 , further comprising a mounting adhesive disposed on at least a portion of a region of the upper surface of the first semiconductor die, at least a portion of the mounting adhesive disposed between the at least one adhesive flow control dam and the second semiconductor die.
29. The stacked semiconductor die assembly of claim 28 , wherein the mounting adhesive is configured to be thermally conductive having an exposed surface area being heat dissipative.
30. The stacked semiconductor die assembly of claim 29 , wherein the mounting adhesive comprises an Ag-filled polymer.
31. The stacked semiconductor die assembly of claim 28 , wherein the mounting adhesive is configured to have a coefficient of thermal expansion selected from a group consisting of a coefficient of thermal expansion of the first semiconductor die, a coefficient of thermal expansion of the second semiconductor die, and an average of the coefficients of thermal expansion of the first semiconductor die and the second semiconductor die.
32. The stacked semiconductor die assembly of claim 25 , wherein the at least one adhesive flow control dam comprises at least one decoupling capacitor coupon.
33. The stacked semiconductor die assembly of claim 32 , wherein an adhesive used to mount the second semiconductor die includes an electrically insulating adhesive.
34. The stacked semiconductor die assembly of claim 25 , wherein the at least one adhesive flow control dam comprises a material selected from a group consisting of polyimides, polyamides, and epoxies.
35. The stacked semiconductor die assembly of claim 25 , wherein the at least one adhesive flow control dam includes a flow control dam more viscous than an adhesive used to adhesively mount the second semiconductor die.
36. The stacked semiconductor die assembly of claim 25 , wherein the first semiconductor die is larger than the second semiconductor die.
37. The stacked semiconductor die assembly of claim 25 , wherein the first semiconductor die is substantially the same size as the second semiconductor die.
38. The stacked semiconductor die assembly of claim 25 , wherein the first semiconductor die comprises an integrated circuit semiconductor die.
39. The stacked semiconductor die assembly of claim 25 , wherein the second semiconductor die comprises an integrated circuit semiconductor die.
40. The stacked semiconductor die assembly of claim 38 , wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.
41. The stacked semiconductor die assembly of claim 39 , wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.
42. The stacked semiconductor die assembly of claim 25 , wherein the first semiconductor die comprises an interposer.
43. The stacked semiconductor die assembly of claim 25 , wherein the second semiconductor die is mounted in an offset fashion relative to the first semiconductor die.
44. The stacked semiconductor die assembly of claim 25 , wherein at least a portion of the second semiconductor die is in contact with the at least one adhesive flow control dam.
45. The stacked semiconductor die assembly of claim 44 , wherein the at least one adhesive flow control dam is configured to deform upon the contact with the second semiconductor die.
46. The stacked semiconductor die assembly of claim 25 , wherein the at least one adhesive flow control dam extends substantially across an entire width of the first semiconductor die.
47. The stacked semiconductor die assembly of claim 25 , further comprising at least one wire bond extending from at least one electrical contact of the plurality of electrical contacts.
48. The stacked semiconductor die assembly of claim 47 , wherein the at least one adhesive flow control dam is further configured to prevent solder flow onto at least a portion of the second semiconductor die or an extension thereof during wire bonding of at least one electrical contact of the plurality of electrical contacts.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 24, 2004
May 29, 2007
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