A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a pattern generation circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a data comparator which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance in accordance with the test pattern and the data output from the circuit to be tested.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A test circuit comprising: a register circuit, into which data is written after data is cleared in compliance with a reset instruction executed by a reset signal, the register circuit holding the written data until a reset instruction is executed by a subsequent reset signal; a first circuit which receives a signal for selecting a test mode to be applied for testing a circuit to be tested, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a second circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a third circuit which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance of the circuit to be tested in accordance with the test pattern and the data output from the circuit to be tested.
2. The test circuit according to claim 1 further comprising: a fourth circuit which outputs a result of the evaluation made by the third circuit to outside in synchronization with the second clock.
3. The test circuit according to claim 1 , wherein the evaluation made by the third circuit is performed by judging whether the test pattern and the data output from the circuit to be tested match or do not match.
4. The test circuit according to claim 1 , wherein the first clock is a clock supplied to the first circuit from outside of the first circuit; and the second clock is a clock supplied to the second and third circuits from outside of the second and third circuits.
5. The test circuit according to claim 1 further comprising: an oscillator which generates the second clock.
6. The test circuit according to claim 1 , wherein the second clock has the same frequency as an actual operating frequency of the circuit to be tested.
7. A semiconductor integrated circuit device comprising: the test circuit of claim 1 , formed on a semiconductor substrate; a logic circuit formed on the semiconductor substrate; a first common wiring which is formed on the semiconductor substrate and connected to both the first circuit of the test circuit and the logic circuit; and a first common terminal which is formed on the semiconductor substrate and connected to the first common wiring.
8. The semiconductor integrated circuit device according to claim 7 , wherein the first common terminal receives the first clock or a third clock for giving a timing of operation of the logic circuit.
9. The semiconductor integrated circuit device according to claim 8 further comprising: a second common wiring which is formed on the semiconductor substrate and connected to both the first circuit of the test circuit and the logic circuit; and a second common terminal which is formed on the semiconductor substrate and connected to the second common wiring, and receives a signal output from the test circuit or a signal output from the logic circuit.
10. The semiconductor integrated circuit device according to claim 7 , wherein the first common terminal receives the signal for selecting a test mode or data for operating the logic circuit.
11. A method for testing a circuit to be tested, using a test circuit including a register circuit, into which data is written after data is cleared in compliance with a reset instruction executed by a reset signal, the register circuit holding the written data until a reset instruction is executed by a subsequent reset signal; the method comprising: supplying the test circuit with a signal for selecting a test mode to be applied for testing a circuit to be tested, and writing the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; generating a test pattern in accordance with the data held in the register circuit, and outputting data based on the test pattern to the circuit to be tested in synchronization with a second clock; and supplying the test circuit with data output from the circuit to be tested in synchronization with the second clock, and making an evaluation of performance of the circuit to be tested in accordance with the test pattern and the data output from the circuit to be tested.
12. The method according to claim 11 , further comprising: outputting a result of the evaluation to outside in synchronization with the second clock.
13. The method according to claim 11 , wherein the evaluation is performed by judging whether the test pattern and the data output from the circuit to be tested match or do not match.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 25, 2005
May 29, 2007
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