Voting circuit

1. A circuit for correcting errors in a signal duplicated N times, wherein N is an integer greater than one, the circuit comprising: a plurality of AND gates, wherein each of the plurality of AND gates comprises a plurality of inputs for receiving a copy of the signal duplicated N times such that each AND gate receives as many copies of the signal as there are AND gates; and an OR gate having a plurality of inputs, wherein each of the plurality of inputs of the OR gate is connected to an output of a corresponding one of the AND gates, wherein an output of the OR gate comprises the corrected signal.

2. The circuit of claim 1 wherein N is greater than or equal to 2 (x+1) , wherein x is a number of corrupted signals.

3. The circuit of claim 2 wherein the plurality of AND gates comprises x+1 AND gates.

4. The circuit of claim 3 wherein each of the plurality of AND gates comprises x+1 inputs.

5. The circuit of claim 2 wherein the OR gate comprises x+1 inputs.

6. The circuit of claim 3 wherein the value of x is one and the value of N is four.

7. The circuit of claim 3 wherein the value of x is two and the value of N is nine.

8. The circuit of claim 3 wherein the value of x is three and the value of N is sixteen.

9. A voting circuit for correcting errors in a signal duplicated N times, wherein N is greater than or equal to 2 (x+1) and x is a number of corrupted signals, the voting circuit comprising: a first circuit logically equivalent to a plurality of AND gates, each comprising a plurality of inputs for receiving a copy of the signal duplicated N times such that each AND gate receives as many copies of the signal as there are AND gates; and a second circuit logically equivalent to an OR gate having a plurality of inputs, wherein each of the plurality of inputs of the second circuit is connected to a corresponding output of an AND gate of the first circuit, wherein an output of the second circuit comprises the corrected signal.

10. The voting circuit of claim 9 wherein the value of x is one and the value of N is four.

11. The voting circuit of claim 9 wherein the value of x is two and the value of N is nine.

12. The voting circuit of claim 9 wherein the value of x is three and the value of N is sixteen.

13. The voting circuit of claim 9 wherein all of the x corrupted signals are input to a single one of the plurality of AND gates of the first circuit.

14. The voting circuit of claim 9 wherein fewer than all of the x corrupted signals are input to a single one of the plurality of AND gates of the first circuit.