A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory interface circuit connecting a memory device and an application device, comprising: a first delay chain including M delay cells, a phase detector and a digital counter, wherein a subset of the M delay cells, the phase detector and the digital counter are used to generate a coarse phase shift control setting; a phase offset control circuit configured to combine the coarse phase shift control setting with one of two residual phase shift control settings, a static residual phase shift control setting and a dynamic residual phase shift control setting, to form a fine phase shift control setting; and a second delay chain including N delay cells that is configured to receive the fine phase shift control setting and the coarse phase shift control setting to produce a desired phase delay in a data sampling signal.
2. The circuit of claim 1 , wherein the phase detector in the first delay chain receives at two input terminals a clock signal without a delay and a clock signal delayed by the subset of delay cells, measures a phase difference between the two signals and submits the phase difference to the digital counter.
3. The circuit of claim 2 , wherein the digital counter updates the coarse phase shift control setting in accordance with the phase difference submitted by the phase detector and applies the updated coarse phase shift control setting to the subset of delay cells.
4. The circuit of claim 1 , wherein the first delay chain includes a programmable switch that selects the number of delay cells in the subset.
5. The circuit of claim 1 , wherein the phase detector in the first delay chain receives both a clock signal without a delay and a clock signal delayed by a set of delay cells in accordance with the coarse phase shift control setting, measures a phase difference between the two signals and submits the phase difference to the digital counter, the digital counter having an output that specifies the coarse phase shift control setting, said coarse phase shift control setting being changed until the phase difference between the two clock signals is substantially close to 360°.
6. The circuit of claim 1 , wherein the phase offset control circuit includes a first programmable switch for choosing one of the static and dynamic residual phase shift control settings and a second programmable switch for choosing one of two instruction bits, each instruction bit being associated with one of the two residual phase shift control settings.
7. The circuit of claim 6 , wherein the phase offset control circuit includes an adder configured to add to or subtract from the coarse phase shift control setting one of the static and dynamic residual phase shift control settings in accordance with its associated instruction bit to generate the fine phase shift control setting.
8. The circuit of claim 1 , wherein the static residual phase shift control setting is stored in a series of configuration flip-flops.
9. The circuit of claim 1 , wherein the dynamic residual phase shift control setting is generated by a soft core calibration logic residing in a programmable logic device.
10. The circuit of claim 1 wherein the second delay chain includes a first programmable switch for choosing one of the coarse and fine phase shift control settings for each delay cell in the second delay chain and a second programmable switch that determines the number of delay cells in the second delay chain.
11. A circuit for generating a signal having a desired phase delay, comprising: a first circuit for generating a coarse phase shift control setting in accordance with the desired phase delay; a second circuit for generating a fine phase shift control setting in accordance with both the desired phase delay and the coarse phase shift control setting; a third circuit comprising a set of delay cells for delaying a signal in accordance with both the coarse and fine phase shift control settings; and a selection circuit for applying to each delay cell either the fine phase shift control setting or the coarse phase shift control setting to produce the desired phase delay in the signal.
12. The circuit of claim 11 , wherein a phase detector in the first circuit receives both a clock signal without a delay and a clock signal delayed by a set of delay cells in accordance with the coarse phase shift control setting, measures a phase difference between the two signals and submits the phase difference to a digital counter having an output that specifies the coarse phase shift control setting, said coarse phase shift control setting being changed until the phase difference between the two clock signals is substantially close to 360°.
13. The circuit of claim 11 , wherein the second circuit includes a first programmable switch for choosing one of a static residual phase shift control setting and a dynamic residual phase shift control setting and a second programmable switch for choosing one of two instruction bits, each instruction bit being associated with one of the two residual phase shift control settings.
14. The circuit of claim 13 , wherein the static residual phase shift control setting and its associated instruction bit are pre-computed based upon at least the desired phase delay and the coarse phase shift control setting and stored in a series of configuration flip-flops, and the dynamic residual phase shift control setting and its associated instruction bit are dynamically determined by a soft core calibration logic based upon at least the desired phase delay and the coarse phase shift control setting.
15. The circuit of claim 13 , wherein the second circuit includes an adder configured to add to or subtract from the coarse phase shift control setting one of the static and dynamic residual phase shift control settings in accordance with its associated instruction bit to generate the fine phase shift control setting.
16. The circuit of claim 13 , wherein the static residual phase shift control setting and its associated instruction bit are pre-computed and stored in a series of configuration flip-flops based upon at least the desired phase delay and the coarse phase shift control setting.
17. The circuit of claim 13 , wherein the dynamic residual phase shift control setting and its associated instruction bit are dynamically determined by a soft core calibration logic based upon at least the desired phase delay and the coarse phase shift control setting.
18. The circuit of claim 11 , wherein a phase detector in the first circuit receives both a clock signal without a delay and a clock signal delayed by a set of delay cells in accordance with the coarse phase shift control setting and generates a phase difference between the two clock signals.
19. The circuit of claim 18 , wherein the phase detector submits the phase difference to a digital counter, said digital counter updating the coarse phase shift control setting in accordance with the phase difference.
20. A method for generating a signal having a desired phase delay, comprising: generating a coarse phase shift control setting using a first set of delay cells, a phase detector, and a digital counter; generating a fine phase shift control setting in accordance with the desired phase delay and the coarse phase shift control setting; and configuring a second set of delay cells in accordance with the coarse and fine phase shift control settings such that a signal passing through the second set of delay cells has the desired phase delay.
21. The method of claim 20 , wherein configuring the second set of delay cells includes configuring one subset of the delay cells by the fine phase shift control setting and configuring another subset of the delay cells by the coarse phase shift control setting.
22. The method of claim 21 , wherein all the delay cells in the second set are configured by the fine phase shift control setting.
23. The method of claim 20 , wherein the generating of the fine phase shift control setting includes: choosing one of a static residual phase shift control setting and a dynamic residual phase shift control setting; choosing one of two instruction bits, the chosen instruction bit being associated with the chosen residual phase shift control setting; and adding to or subtracting from the coarse phase shift control setting the chosen residual phase shift control setting in accordance with the chosen instruction bit to generate the fine phase shift control setting.
24. The method of claim 23 , wherein the static residual phase shift control setting and its associated instruction bit are pre-computed based upon the desired phase delay and the coarse phase shift control setting and stored in a series of configuration flip-flops, and the dynamic residual phase shift control setting and its associated instruction bit are dynamically determined based upon the desired phase delay and the coarse phase shift control setting in accordance with a calibration algorithm.
25. The method of claim 23 , wherein the static residual phase shift control setting and its associated instruction bit are pre-computed and stored in a series of configuration flip-flops based upon at least the desired phase delay and the coarse phase shift control setting.
26. The method of claim 23 , wherein the dynamic residual phase shift control setting and its associated instruction bit are dynamically determined by a soft core calibration logic based upon at least the desired phase delay and the coarse phase shift control setting.
27. The method of claim 20 , wherein the phase detector receives at two input terminals a clock signal without a delay and a clock signal delayed by the first set of delay cells in accordance with the coarse phase shift control setting measures a phase difference between the two signals and submits the phase difference to the digital counter, which, in turn, updates the coarse phase shift control setting until the phase difference between the two clock signals is substantially close to 360°.
28. The method of claim 20 , wherein a phase detector receives at two input terminals both a clock signal without a delay and a clock signal delayed by the first set of delay cells in accordance with the coarse phase shift control setting and generates a phase difference between the two clock signals.
29. The method of claim 28 , wherein the phase detector submits the phase difference to a digital counter, said digital counter updating the coarse phase shift control setting in accordance with the phase difference.
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February 9, 2005
June 5, 2007
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