A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the wordline. Additionally, a voltage pump can supply operating voltage to the inverter to assist in overdriving the wordline. A voltage sink can also be coupled to the inverter which, in combination with the voltage pump, can be used to shift the output voltages used to turn the wordline on and off. A second inverter can also be added, and in such a case the transistors within the latch and the first inverter can be reduced in size, switching time, and power consumption.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of operating a wordline decoder, comprising: receiving and decoding wordline address information and setting a latch associated with a wordline to a predetermined state when an address of said wordline is decoded; supplying a voltage from a voltage pump to a first output inverter for turning on said wordline; providing a signal by said first output inverter in response to the state of said latch being set to said predetermined state; driving a signal line with said signal provided by said first output inverter; driving said selected wordline with a second output inverter having an input connected to an output of said first output inverter; and driving said selected wordline with said second output inverter to a voltage below ground when turning off said wordline.
2. The method of claim 1 , wherein a size of a pair of cross-coupled transistors within said latch is chosen so as to minimize power consumption.
3. The method of claim 1 , further comprising: shifting output levels of said first output inverter between a pumped voltage a potential lower than ground.
4. The method of claim 1 , further comprising: supplying a voltage sink to said second output inverter for turning off said wordline.
5. The method of claim 1 , wherein a size of a pair of complementary transistors within said output inverter is chosen to have maximum switching speed while still minimizing power consumption.
6. A method of operating a wordline decoder, comprising: receiving and decoding wordline address information and setting a latch associated with a wordline to a predetermined state when an address of said wordline is decoded; providing a signal by a first output inverter in response to the state of said latch being set to said predetermined state; driving a signal line with said signal provided by said first output inverter; shifting output levels of said first output inverter between a pumped voltage and a potential lower than ground; driving said selected wordline with a second output inverter having an input connected to an output of said first output inverter; and driving said selected wordline with said second output inverter to a voltage below ground when turning off said wordline.
7. The method of claim 6 , wherein a size of a pair of cross-coupled transistors within said latch is chosen so as to minimize power consumption.
8. The method of claim 6 , further comprising: supplying a voltage sink to said second output inverter for turning off said wordline.
9. The method of claim 6 , wherein a size of a pair of complementary transistors within said output inverter is chosen to have maximum switching speed while still minimizing power consumption.
10. The method of claim 6 , further comprising: supplying a voltage by a voltage pump to said first output inverter.
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November 29, 2005
June 5, 2007
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