Patentable/Patents/US-7232362
US-7232362

Chemical mechanical polishing process for manufacturing semiconductor devices

PublishedJune 19, 2007
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A chemical-mechanical polishing (CMP) process for the manufacturing of semiconductor devices is disclosed. The process includes removing a first portion of a first layer of interconnect materials using a first platen and a first slurry, removing a second portion of the first layer using a second platen and a second slurry, removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry, and removing a second portion of the second layer using a third platen and a fourth slurry.

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for forming an interconnect structure of a semiconductor device utilizing a chemical-mechanical polishing (CMP) processing, comprising: removing a first portion of a first layer of interconnect materials using a first platen and a first slurry; removing a second portion of the first layer using a second platen and a second slurry; removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry; and removing a second portion of the second layer using a third platen and a fourth slurry.

2

2. The method of claim 1 wherein the first layer comprises a conductive layer.

3

3. The method of claim 1 wherein the first layer comprises copper (Cu).

4

4. The method of claim 1 wherein the second layer comprises a barrier layer.

5

5. The method of claim 1 wherein the second layer comprises tantalum (Ta).

6

6. The method of claim 1 wherein the thickness of the first portion of the second layer is approximately 10 Angstroms.

7

7. The method of claim 1 wherein the thickness of the first portion of the second layer is approximately 300 Angstroms.

8

8. The method of claim 1 wherein the thickness of the first portion of the second layer is between approximately 10 Angstroms to approximately 300 Angstroms.

9

9. The method of claim 1 wherein removing a first portion of a second layer of the interconnect materials comprises a slower polishing operation than removing a second portion of the first layer.

10

10. The method of claim 9 wherein the slower polishing operation utilizes a polishing pressure of between about 0.2 psi to about 8 psi.

11

11. The method of claim 1 wherein the second slurry comprises silica.

12

12. The method of claim 1 wherein the third slurry comprises alumina.

13

13. The method of claim 9 wherein the slower polishing operation utilizes a lower platen rotation speed and a lower slurry dispensing speed.

14

14. The method of claim 1 wherein the fourth slurry comprises silica.

15

15. A method for forming an interconnect structure of a semiconductor device using a multi-platen chemical mechanical polishing (CMP) process, comprising: removing a first portion of a copper (Cu) layer of interconnect materials using a first platen and a first slurry; removing a second portion of the Cu layer using a second platen and a second slurry; removing a first portion of a tantalum (Ta) layer of the interconnect materials using a second platen and a third slurry, wherein the thickness of the first portion is between approximately 10 Angstroms to approximately 300 Angstroms; and removing a second portion of the Ta layer using a third platen and a fourth slurry.

16

16. The method of claim 15 wherein removing a first portion of a tantalum layer of the interconnect materials comprises a slower polishing operation than removing a second portion of the Cu layer.

17

17. The method of claim 16 wherein the slower polishing operation utilizes a polishing pressure of between about 0.2 psi to about 8 psi.

18

18. The method of claim 15 wherein the first slurry comprises silica.

19

19. The method of claim 15 wherein the second slurry comprises alumina.

20

20. A method for forming an interconnect structure of a semiconductor device utilizing a chemical-mechanical polishing (CMP) processing, comprising: removing a first portion of a first layer of interconnect materials using a first platen and a first slurry; removing a second portion of the first layer using a second platen and a second slurry; removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry; and removing a second portion of the second layer using a third platen and the third slurry.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

October 12, 2004

Publication Date

June 19, 2007

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “Chemical mechanical polishing process for manufacturing semiconductor devices” (US-7232362). https://patentable.app/patents/US-7232362

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.