A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processor based built-in self test system contained in an integrated circuit chip having an embedded DRAM, said embedded DRAM including a multiplicity of DRAM blocks, said test system comprising: means for generating a test data pattern; means for writing said test data pattern into each DRAM block simultaneously; means for reading out sequentially from a first DRAM block to a last DRAM block of said multiplicity of DRAM blocks a resultant data pattern from each said DRAM block of said multiplicity of DRAM blocks after a predetermined period of time has elapsed from said writing of said test data into each said DRAM block of said multiplicity of DRAM blocks, said means for reading further including means for completing the reading of any previous DRAM block of said multiplicity of DRAM blocks before the reading of a subsequent DRAM block of said multiplicity of DRAM blocks; means for storing scan out data for each said DRAM block, said scan out data comprising said resultant data pattern or information based on said resultant data pattern of each said DRAM block; and means for scanning out said scan out data, said means for scanning including means for completing scanning out of any previous scan out data for a previous DRAM block of said multiplicity of DRAM blocks before scanning in of scan out data for a subsequent DRAM block of said multiplicity of DRAM blocks.
2. The test system of claim 1 , further including: means for comparing said resultant data pattern with said test data pattern; and means for creating redundancy allocation information based on the comparison between said resultant data pattern and said test data pattern.
3. The test system of claim 2 , wherein said scan out data comprises said redundancy allocation information.
4. The test system of claim 1 , wherein said means for storing scan out data comprises a register.
5. The test system of claim 1 , further including: means for comparing said resultant data pattern with said test data pattern and for creating redundancy allocation information based on the comparison between said resultant data pattern and said test data pattern and storing; and a redundancy allocation register for storing said redundancy allocation information.
6. The test system of claim 5 , further including: means for scanning out said redundancy allocation information from said redundancy allocation register.
7. The test system of claim 5 , wherein said means for storing scan out data comprises a register and further including means for scanning in fuse delete information based on said redundancy allocation information into said store register.
8. A processor based built-in self test system contained in an integrated circuit chip having an embedded DRAM, said embedded DRAM including a multiplicity of DRAM blocks, said test system comprising: means for generating a test data pattern; means for writing said test data pattern into each DRAM block sequentially from a first DRAM block to a last DRAM block of said multiplicity of DRAM blocks, said means for writing including means for completing writing of a previous DRAM block before the start of writing of a subsequent DRAM block of said multiplicity of DRAM blocks; means for reading out a resultant data pattern from each said DRAM block sequentially from a first DRAM block to a last DRAM block of said multiplicity of said DRAM blocks after a predetermined period of time has elapsed from said writing of said test data into each said DRAM block, said means for reading including means for completing reading of any previous DRAM block of said multiplicity of DRAM blocks before starting reading of a subsequent DRAM block of said multiplicity of DRAM blocks; means for storing scan out data for each said DRAM block, said scan out data comprising said resultant data pattern or information based on said resultant data pattern of each said DRAM block, said means for storing including means for completing storing of scan out data for a previous DRAM block of said multiplicity of DRAM blocks before starting storing of scan out data for a subsequent DRAM block of said multiplicity of said DRAM blocks.
9. The test system of claim 8 further including: means for comparing said resultant data pattern with said test data pattern; and means for creating redundancy allocation information based on the comparison between said resultant data pattern and said test data pattern.
10. The test system of claim 9 , further including means for writing back fuse delete information based on said redundancy allocation information into said multiplicity of store registers.
11. The test system of claim 9 , wherein said scan out data comprises said redundancy allocation information.
12. The test system of claim 8 , wherein said means for storing scan out data comprises a multiplicity of store registers.
13. The test system of claim 12 , wherein there is a respective store register of said store registers for each DRAM blocks of said multiplicity of DRAM blocks.
14. The test system of claim 12 , further including means for scanning out said scan out data from said multiplicity of store registers sequentially, said means for scanning out said scan out data including means for completing scanning out of any scan out data of a previous store register of said multiplicity of store registers before starting scanning out of scan out data of a subsequent store register of said multiplicity of store registers.
15. The test system of claim 12 , wherein a number of said store registers of said multiplicity of store registers is equal to the number of said DRAM blocks of said multiplicity of DRAM blocks.
16. The test system of claim 12 , wherein said means for means for storing said scan out data for each said DRAM block on said multiplicity of store registers includes a redundancy allocation register coupled to a redundancy allocation store device, said redundancy allocation store device including an interface shift register coupled to each said store register of said multiplicity of store registers.
17. The test system of claim 16 , further including means for writing the contents of said interface shift register into a previous store register of said multiplicity of store registers as the contents of a subsequent store register of said multiplicity of store registers are simultaneously written into said interface shift register.
18. The test system of claim 13 , further including means for simultaneously swapping the state of latches within said redundancy allocation register with the state of latches within said interface shift register.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 22, 2004
June 26, 2007
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