Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for producing a semiconductor memory device having a memory array structure comprising: a plurality of charge storage regions formed on a main surface of a first conductor type semiconductor substrate through a first insulator; a plurality of word lines formed on said plurality of charge storage regions through a second insulator; wherein said method includes the following steps: (a) forming a first conductor film for said plurality of word lines on said second insulator, then forming a third insulator on said first conductor film; (b) patterning said third insulator and said first conductor film, thereby forming a plurality of first word lines within a space therebetween; (c) subjecting said semiconductor substrate to a thermal oxidation process to form a side spacer on a side face of each of said plurality of first word lines; and (d) embedding a second conductor film for word lines in each of said space regions after said step (c) so as to form a plurality of second word lines in each of said plurality of space regions.
2. The method for producing a memory device according to claim 1 , wherein said step (d) is divided into a first sub-step for forming said second conductor film on said semiconductor substrate that includes each of said plurality of space regions and a second sub-step of flattening the surface of said second conductor film by a chemical mechanical polishing method after said first step using said third insulator that covers the top face of each of said plurality of word lines as a stopper film.
3. The method for producing a semiconductor memory device according to claim 1 , wherein the space between each first word line and each second word line that are adjacent to each other is ½ of their width and under.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 14, 2005
July 3, 2007
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