Semiconductor memory device

1. A semiconductor memory device comprising: means for generating a refresh address for a memory array including a plurality of cells, each of which needs refreshing for data retention; means for deciding on whether or not said refresh address generated corresponds to an address to be interrupted by a row address whose refresh period is subject to change; and means for performing control for interrupting the generated refresh address to output said row address whose refresh period is subject to change, if the result of decision indicates that the generated refresh address is the address to be interrupted by said row address whose refresh period is subject to change.

2. The semiconductor memory device according to claim 1 , further comprising: means for deciding on whether or not said generated refresh address corresponds to an address for which refreshing this time is to be skipped over; and means for skipping over the refreshing of said generated refresh address in case the result of decision indicates that said generated refresh address corresponds to an address for which refreshing is to be skipped over.

3. A semiconductor memory device comprising: a counter for generating a refresh address for a memory array including a plurality of cells, each of which needs refreshing for data retention; storage means for storing information as to whether or not an output of said counter corresponds to an address to be interrupted by a row address whose refresh period is subject to change in association with a count value; control means for performing control so that, if the output of said counter corresponds to the address to be interrupted by said row address whose refresh period is subject to change, said counter output is interrupted by said row address whose refresh period is subject to change, and said row address whose refresh period is subject to change is used as a refresh address for said memory array in place of said counter output.

4. The semiconductor memory device according to claim 3 , wherein the row address whose refresh period is subject to change is output a plural number of times during the time said counter makes a round of count operation.

5. The semiconductor memory device according to claim 4 , wherein said row address whose refresh period is subject to change includes at least a row address output M times, where M is an integer not less than two, and a row address output N times, where N is an integer different than M and is not less than two, during the time said counter makes a round of count operation.

6. The semiconductor memory device according to claim 3 , wherein said row address whose refresh period is subject to change includes a row address output once during the time said counter makes a plurality of rounds of count operations.

7. The semiconductor memory device according to claim 3 , wherein said counter performs count operation, responsive to a refresh command received or to a trigger signal generated on timeout in a refresh timer.

8. The semiconductor memory device according to claim 3 , wherein said counter output is output as a refresh address in a cycle next following the cycle in which the row address whose refresh period is subject to change is output as a refresh address to interrupt said counter output.

9. The semiconductor memory device according to claim 3 , further comprising: at least one set of a storage unit for storing a count value which is to be interrupted by a row address whose refresh period is subject to change, and a comparator circuit for comparing said count value stored in said storage unit and an output of said counter to each other; a holding circuit for setting an output hit signal to an active state when a coincidence signal from said comparator circuit is output; said holding circuit resetting said hit signal to an inactive state in the next clock cycle; a circuit for receiving an output of said holding circuit and a refresh clock signal, and for performing control so that, when said hit signal is in an active state, said refresh clock signal is not propagated to said counter to halt the count operation thereof, and so that, when said hit signal is in an inactive state, said refresh clock signal is propagated to said counter; and a circuit for modifying at least a part of said counter output when said hit signal is in an active state to generate the row address which refresh period is subject to change.

10. The semiconductor memory device according to claim 9 , further comprising: a plurality of sets of said storage units and said comparator circuits; and a circuit for generating a coincidence signal based on the logical sum of outputs of said plural comparator circuits to supply said coincidence signal generated to said holding circuit.

11. The semiconductor memory device according to claim 3 , further comprising: a storage unit for storing said row address whose refresh period is subject to change; a comparator circuit for comparing the row address stored in said storage unit and an output of said counter to each other; said comparator circuit including a first comparator circuit section for comparing an upper bit set of said counter output and an upper bit set of a count value of said storage unit, and a second comparator circuit section for comparing lower bits of said counter output and lower bits of said row address which refresh period is subject to change; a coincidence decision circuit for giving a decision for coincidence when the result of comparison by said first comparator circuit section indicates non-coincidence and the result of comparison by said second comparator circuit section indicates coincidence; a holding circuit for setting an output hit signal to an active state, responsive to the result of coincidence decision by said coincidence decision circuit and for resetting said hit signal to an inactive state, in the next following clock cycle; a circuit for receiving said hit signal output from said holding circuit and a refresh clock signal and for performing control so that, when said hit signal in an active state, said refresh clock signal is not propagated to said counter to halt the count operation thereof, and so that, when said hit signal is in an inactive state, said refresh clock signal is propagated to said counter; and a circuit for modifying at least a part of said count output of said counter when said output hit signal is in an activate state to generate said row address which refresh period is subject to change.

12. The semiconductor memory device according to claim 11 , wherein said circuit generating the row address which refresh period is subject to change includes a selector circuit; said selector circuit receiving said hit signal as a selection control signal and outputting an upper bit set of said counter output when said hit signal is in an inactive state; said selector circuit outputting, when said hit signal is in an activate state, an upper bit set of said row address whose refresh period is subject to change, stored in said storage unit and determined to be coincident.

13. The semiconductor memory device according to claim 11 , further comprising: a plurality of sets each composed of said comparator circuit, made up by said first comparator circuit section and said second comparator circuit section, and of said storage unit; a circuit for generating a first comparison result signal, based on a logical sum of said plural first comparator circuit sections, to supply said first comparison result signal generated to said holding circuit; and a circuit for generating a second comparison result signal, based on a logical sum of said plural second comparator circuit sections, to supply said second comparison result signal generated to said holding circuit; said coincidence decision circuit for giving a decision for coincidence when said first comparison result signal indicates non-coincidence and said second comparison result signal indicates coincidence.

14. The semiconductor memory device according to claim 11 , wherein said upper bit set is the most significant bit of the counter output and said lower bits comprises the counter output other than said most significant bit.

15. The semiconductor memory device according to claim 11 , wherein said upper bit set is comprised of a preset number of upper bits of the counter output as counted from the MSB side and said lower bits comprises the counter output other than said upper-bits.

16. The semiconductor memory device according to claim 3 , further comprising: a storage unit for receiving an output of said counter as an address, said storage unit storing in a cell thereof to be accessed by said address information indicating whether said counter output is to be interrupted by said row address which refresh period is subject to change or to be directly output as a refresh address; a holding circuit for setting a hit signal to an active state when said information indicates that an output of said storage unit is to be interrupted by said row address which refresh period is subject to change and for resetting said hit signal to an inactive state in the next following clock cycle; a circuit for receiving an output of said holding circuit and a refresh clock signal and for performing control so that, when said hit signal is in an active state, said refresh clock signal is not propagated to said counter to halt the count operation thereof, and so that, when said hit signal in an inactive state, said refresh clock signal is propagated to said counter; and a circuit for modifying at least a part of said counter output to generate said row address which refresh period is subject to change, when said hit signal is in an activate state.

17. The semiconductor memory device according to claim 3 , further comprising: a storage unit for receiving an output of said counter as an address, said storage unit storing in a cell thereof to be accessed by said address information as to whether said counter output is to be directly output as a refresh address or is to be replaced by said row address which refresh period is subject to change, and bit manipulation information specifying the operation on bits in order to effect bit replacement if such bit replacement is to be made; a coincidence decision circuit for outputting a coincidence signal in case an output of said storage unit indicates that said counter output is to be replaced by said row address which refresh period is subject to change; a holding circuit for setting an output hit signal to an active state, when said coincidence decision circuit makes a decision for coincidence, and for resetting said hit signal to an inactive state in the next following clock cycle; a circuit for receiving said hit signal output from said holding circuit and a refresh clock signal; said circuit performing control so that, when said hit signal is in an active state, said refresh clock signal is not propagated to said counter to halt the count operation thereof, and so that, when said hit signal is in an inactive state, said refresh clock signal is propagated to said counter; and a circuit for executing bit-manipulation on the counter output and modifying at least a part thereof, based on said bit manipulation information output from said storage unit, to generate said row address which refresh period is subject to change.

18. The semiconductor memory device according to claim 3 , further comprising: a storage unit for receiving an output of said counter as an address, said storage unit storing in a cell thereof to be accessed by said address the first information as to whether or not said counter output is to be replaced by said row address which refresh period is subject to change and the second information as to whether or not refresh having an output of said counter as a refresh address is to be skipped over; a holding circuit for setting an output hit signal to an active state based on the first and second information output from said storage unit and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit for receiving said hit signal output from said holding circuit and a refresh clock signal; said circuit performing control so that, when said hit signal is in an active state, said refresh clock signal is not propagated to said counter to halt the count operation thereof, and so that, when said hit signal is in an inactive state, said refresh clock signal is propagated to said counter; a circuit for halting the refresh operation based on said second information output from said storage unit and on a preset bit signal of said counter output to halt the refresh operation; and a circuit for modifying at least a part of said counter output to generate said row address which refresh period is subject to change, when said hit signal is in an activate state.

19. The semiconductor memory device according to claim 18 , wherein the bit width of said counter output is larger by at least one bit than the bit width of the refresh address.

20. The semiconductor memory device according to claim 3 , wherein said control means performs control so that the refreshing using as a refresh address said counter output interrupted by said row address whose refresh period is subject to change is executed in the next cycle following the refreshing using as a refresh address said row address whose refresh period is subject to change.