A chip package is formed which has an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another to permit a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a chip package, comprising the steps of: a. providing a lead frame of predetermined thickness having an upwardly facing surface and a downwardly facing surface, a central region having a first plurality of sides, and a peripheral edge region having a second plurality of sides extending around and spaced from said first plurality of sides; b. providing an upper mask to position resist material on said upwardly facing surface that define a first set of leads extending from each of said second plurality of sides, each of said first set of leads being partially defined by a first terminal end, first opposing side surfaces each of which extends along a respective first longitudinal axis, and a lower surface that extends in a first plane; c. providing a lower mask to position resist material on said downwardly facing surface that define a second set of leads extending from said second plurality of sides, each of said second set of leads being partially defined by a second terminal end, second opposing side surfaces each of which extends along a respective second longitudinal axis, and an upper surface that extends in a second plane, and a portion of said second set of leads that are vertically aligned with a portion of said first set of leads; d. etching away portions of said upwardly facing surface that are not covered with said resist material to a depth greater than one half of said predetermined thickness; and e. etching away portions of said downwardly facing surface that are not covered with said resist material to a depth greater than one half of said predetermined thickness, wherein each of said first set of leads are positioned in non-overlapping staggered relation to corresponding ones of said second set of leads such that said first terminal ends are spaced from said second terminal ends by a first predetermined distance, each of said first longitudinal axes are substantially parallel to and spaced from the adjacent ones of said second longitudinal axes by a second predetermined distance, and said first plane is spaced from said second plane by a third predetermined distance.
2. The method according to claim 1 , comprising the further step of encapsulating said chip carrier package in a resin.
3. The method according to claim 2 , comprising the further step of removing said peripheral edge.
4. The method according to claim 3 , wherein said step of removing said peripheral edge is by saw singulation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 16, 2004
August 7, 2007
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