Patentable/Patents/US-7262122
US-7262122

Method of forming metal line in semiconductor memory device

PublishedAugust 28, 2007
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

The present invention relates to a method of forming a metal line of a semiconductor memory device. According to the present invention, after a drain contact plug formed within an interlayer insulating film protrudes, a nitride film is formed on the top of the drain contact plug, and a trench etch process is then performed using the nitride film as an etch-stop layer. Therefore, loss of the interlayer insulating film formed between a source contact plug and a metal line can be prevented, and generation of a short circuit between the metal line and the source contact plug can also be prevented.

Patent Claims
10 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of forming a metal line of a semiconductor memory device, comprising the steps of: providing a semiconductor substrate in which a source contact plug is formed in a source contact hole of a first interlayer insulating film; forming a second interlayer insulating film on the semiconductor substrate; patterning the second interlayer insulating film by performing an etch process using a drain contact mask, thus forming a drain contact hole through a drain region formed within the semiconductor substrate; forming a drain contact plug to bury the drain contact hole; recessing the second interlayer insulating film through a first etch process, so that the drain contact plug protrudes; depositing a nitride film along the topography on the entire structure including the drain contact plug; forming a third interlayer insulating film on the nitride film; patterning the third interlayer insulating film so that the nitride film formed on the protruded portion of the drain contact plug is exposed, thereby forming a trench; performing a second etch process to strip the nitride film exposed through the trench, thus exposing the drain contact plug; and forming a metal line to bury the trench.

2

2. The method as claimed in claim 1 , wherein the first etch process is set to a condition in which an etch rate of the second interlayer insulating film is at least three times faster than that of the drain contact plug.

3

3. The method as claimed in claim 1 , wherein the first etch process is performed using a BOE or DHF solution.

4

4. The method as claimed in claim 3 , wherein the BOE solution uses a mixed solution of HF and NH 4 F diluted with H 2 O at the ratio of 100:1 to 9:1 in the case where the second interlayer insulating film is formed using a PE-TEOS film.

5

5. The method as claimed in claim 3 , wherein the DHF solution uses HF diluted with H 2 O at the ratio of 100:1 to 50:1 in the case where the second interlayer insulating film is formed using a PE-TEOS film.

6

6. The method as claimed in claim 1 , wherein the drain contact plug protrudes about 300 to 100 Å in thickness.

7

7. The method as claimed in claim 1 , wherein the second etch process is performed in a dry or a wet mode.

8

8. The method as claimed in claim 7 , comprising performing the second etch process in the dry mode using a mixed gas including CF 4 , CHF 3 , O 2 and Ar gases.

9

9. The method as claimed in claim 7 , comprising performing the second etch process in the wet mode at an etch rate of about 40 to 60 Å/min using a H 3 PO 4 solution.

10

10. The method as claimed in claim 1 , wherein the etch process is performed in such a manner that the third interlayer insulating film deposited around the drain contact plug is recessed from the top of the nitride film in thickness of 200 to 300 Å.

Classification Codes (CPC)

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Patent Metadata

Filing Date

June 6, 2005

Publication Date

August 28, 2007

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Cite as: Patentable. “Method of forming metal line in semiconductor memory device” (US-7262122). https://patentable.app/patents/US-7262122

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