System and method for adjusting the phase of a frequency-locked clock

1. A method for adjusting the phase of a frequency locked clock signal, comprising: (a) receiving a target phase offset; (b) setting a remaining phase offset equal to the target phase offset; (c) determining whether providing the sum of the remaining phase offset and a frequency control word to a numerically controlled oscillator would cause the numerically controlled oscillator to overflow, (d) if the numerically controlled oscillator would overflow using the remaining phase offset, computing a phase adjustment factor that is a fraction of the remaining phase offset that will prevent the numerically controlled oscillator from overflowing and computing a new remaining phase offset that equals the present remaining phase offset less the phase adjustment factor, then proceeding to step (f); (e) if the numerically controlled oscillator would not overflow using the remaining phase offset, setting a phase adjustment factor to be equal to the remaining phase offset; (f) adding the phase adjustment factor to a frequency control word to create a modified frequency control word; (g) providing the modified frequency control word to a numerically controlled oscillator; (h) generating an output signal of the numerically controlled oscillator based on the modified frequency control word; and (i) if the phase adjustment factor was set to a value other than the remaining phase offset in step (e), repeating steps (c) through steps (i).

2. A method for adjusting the phase of a frequency locked clock signal, comprising: (a) receiving a target phase offset; (b) setting a remaining phase offset equal to the target phase offset; (c) determining whether providing the sum of the remaining phase offset and a frequency control word to a numerically controlled oscillator would cause the numerically controlled oscillator to underflow; (d) if the numerically controlled oscillator would underflow using the remaining phase offset, computing a phase adjustment factor that is a fraction of the remaining phase offset that will prevent the numerically controlled oscillator from underflowing and computing a new remaining phase offset that equals the present remaining phase offset less the phase adjustment factor, then proceeding to step (f); (e) if the numerically controlled oscillator would not underflow using the remaining phase offset, setting a phase adjustment factor to be equal to the remaining phase offset; (f) adding the phase adjustment factor to a frequency control word to create a modified frequency control word; (g) providing the modified frequency control word to a numerically controlled oscillator; (h) generating an output signal of the numerically controlled oscillator based on the modified frequency control word; and (i) if the phase adjustment factor was set to a value other than the remaining phase offset in step (e), repeating steps (c) through steps (i).

3. A clock signal regeneration system to adjust the phase of a frequency-locked clock signal, comprising: (a) a multiplexer for receiving a target phase offset and a remaining phase offset, and for outputting either said target phase offset or said remaining phase offset based on a load new target indicator; (b) a second clock for generating a second clock output signal; (c) at least one register for receiving an output from said multiplexer and the second clock output signal, and for storing said remaining phase offset; (d) a saturator for receiving the output of said at least one register and for providing a phase adjustment factor that is a fraction of the remaining phase offset to a first adder; (e) a second adder for adding the output of said at least one register and said saturator and for providing a resulting remaining phase offset to said multiplexer; (f) said first adder for adding a frequency control word and the phase adjustment factor; (g) a first clock for providing a clock pulse; and (h) a numerically controlled oscillator for receiving an output from said first adder and an output from said first clock for generating an output clock signal.

4. The clock signal regeneration system of claim 3 , further comprising a converter for converting a message containing instructions for the phase adjustment to the target phase offset in a proper format that provides the target phase offset to said multiplexer.

5. A clock signal regeneration system to adjust the phase of a frequency-locked clock signal, comprising: (a) a multiplexer for receiving as inputs a target fractional phase offset and a remaining fractional phase offset, and for outputting either said target fractional phase offset or said remaining fractional phase offset based on a load new target indicator; (b) a second clock for generating a second clock output signal; (c) at least one register for receiving an output from said multiplexer and the second clock output signal, and for storing said remaining fractional offset; (d) a saturator for receiving the output of said at least one register and for providing a fractional phase adjustment factor that is a fraction of said remaining fractional phase offset (e) a second adder for adding the output of said at least one register and said saturator and for providing a remaining fractional phase offset to said multiplexer; (f) a converter for manipulating the output of said saturator and for providing a resulting phase adjustment factor to a first adder; (g) said first adder for adding a frequency control word and the phase adjustment factor; (h) a first clock for providing a clock pulse; and (i) a numerically controlled oscillator for receiving an output from said first adder and an output from said first clock for generating an output clock signal.

6. The clock signal regeneration system of claim 5 wherein said converter is a multiplier that multiplies the output of said saturator and a period of the numerically controlled oscillator and for providing a resulting phase adjustment factor to said first adder.