A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a semiconductor chip having a plurality of bond pads; a leadframe comprising a base metal and having a plurality of lead segments, each of said segments having a first end near said chip and a second end remote from said chip; electrical interconnections between said chip bond pads and said first segment ends, respectively; encapsulation material covering said chip, interconnections and first segment ends, yet leaving said second segment ends exposed; and at least portions of said second segment ends having said base metal covered by a stack of a solderable metal layer and an outermost noble metal layer.
2. The device according to claim 1 wherein said base metal is selected from a group consisting of copper, copper alloy, aluminum, iron-nickel alloy, and covar.
3. The device according to claim 1 wherein said encapsulation material is a molding compound.
4. The device according to claim 1 wherein said solderable metal comprises nickel or a nickel alloy.
5. The device according to claim 1 wherein said outermost layer comprises palladium.
6. The device according to claim 1 wherein said outermost layer comprises gold.
7. The device according to claim 1 wherein said outermost layer is a stack of a palladium layer, in contact with said solderable metal, and a gold layer, in contact with said palladium layer.
8. The device according to claim 1 further comprising a layer of a bondable metal on each of said first segment ends.
9. The device according to claim 8 wherein said bondable metal is silver.
10. The device according to claim 1 wherein said electrical interconnections between said chip bond pads and said first segment ends are bonding wires.
11. The device according to claim 1 wherein said electrical interconnections between said chip bond pads and said first segment ends are reflow metal elements.
12. A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor chip having a plurality of bond pads; providing a leadframe comprising a base metal and having a plurality of lead segments, each of said segments having a first end near said chip and a second end remote from said chip; electrically connecting said chip bond pads with said first segment ends, respectively; encapsulating said chip, interconnections, and first segment ends, yet leaving said second segment ends exposed; electrolytically plating said base metal of said second segment ends with a layer of solderable metal, followed by a layer of noble metal; and trimming and forming said second segment ends.
13. The method according to claim 12 further comprising the steps of: deflashing and cleaning said exposed second segment ends after said step of encapsulating; and activating said exposed second segment ends before said step of electrolytically plating.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 9, 2004
September 11, 2007
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