Programming and erasing method for charge-trapping memory devices

1. A method for programming and erasing charge-trapping memory devices comprising: applying a first negative voltage to a gate causing electron detrapping; applying a positive voltage to the gate following the application of the first negative voltage; and applying a second negative voltage to the gate following the application of the positive voltage.

2. A method as recited in claim 1 , wherein applying the positive voltage to the gate causing electron injection from a channel.

3. A method as recited in claim 2 , wherein applying the positive voltage to the gate causing electron injection into a trapping layer.

4. A method as recited in claim 3 , wherein applying the positive voltage to the gate causes electron tunneling into the trapping layer.

5. A method as recited in claim 1 , wherein the first negative voltage to the gate resets the memory device.

6. A method as recited in claim 5 , wherein the first negative voltage to the gate is in the range from about −15V to about −23V.

7. A method as recited in claim 1 , wherein the positive voltage to the gate is in the range from about 14 to about 20V.

8. A method as recited in claim 5 , wherein the device is reset by Fowler-Nordheim (FN) gate injection.

9. A method as recited in claim 1 , further comprising: erasing the charge-trapping memory devices by applying the second negative voltage to the gate.