A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> semiconductor-on-insulator substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a portion of a semiconductor device structure comprising: providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate; forming a first isolation trench within the semiconductor active layer, depositing a stressor material on a bottom of the first isolation trench, wherein the stressor material includes a dual-use film; and forming a second isolation trench within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench, and wherein the presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> channel orientation of the semiconductor-on-insulator substrate.
2. The method of claim 1 , wherein the dual-use film comprises a nitride layer formed at the bottom of the first isolation trench to prevent a trench liner induced compressive stress and to enable differential stress on a specific device and orientation.
3. The method of claim 1 , wherein forming the first isolation trench and forming the second isolation trench comprises using a 248 nm and a 193 nm dual trench photo process, respectively, wherein the dual-use film provides an optimized reflectivity for both wavelengths.
4. The method of claim 1 , wherein forming the first isolation trench includes using a first wavelength patterning and etch process.
5. The method of claim 4 , further wherein the first wavelength patterning and etch process includes a 248 nm deep ultra violet patterning and etch process.
6. The method of claim 1 , wherein the semiconductor-on-insulator substrate further includes a pad oxide layer overlying the semiconductor active layer and a silicon nitride layer overlying the pad oxide layer, wherein forming the first isolation trench further includes forming the first isolation trench through the silicon nitride layer, the pad oxide, and the semiconductor active layer, and wherein depositing the stressor material includes selectively depositing the dual-use film overlying a bottom of the first isolation trench and overlying a remainder of the silicon nitride layer.
7. The method of claim 1 , wherein the dual-use film comprises a material suitable for use as a stressor material and as an anti-reflective coating.
8. The method of claim 7 , further wherein the dual-use film comprises a nitride.
9. The method of claim 1 , wherein forming the second isolation trench includes using a second wavelength patterning and etch process, wherein the second wavelength is a wavelength different from the first wavelength.
10. The method of claim 9 , wherein the second wavelength patterning and etch process includes a 193 nm deep ultra violet patterning process.
11. The method of claim 1 , further comprising: forming trench liners in respective ones of the first and second isolation trenches along sidewall portions of the first and second isolation trenches.
12. The method of claim 11 , wherein the dual-use film overlying the bottom of the first isolation trench prevents a trench liner in the first isolation trench from extending completely along the sidewall of the first isolation trench, the trench liner extending from a top portion of the sidewall to a lower sidewall portion, where the lower sidewall portion contacts a top portion of the dual-use film within the first isolation trench.
13. The method of claim 11 , wherein the trench liner in the second isolation trench extends completely along the sidewall of the second isolation trench, from a top portion of the sidewall to a bottom portion of the sidewall.
14. The method of claim 11 , wherein the trench liners comprise thermally grown liners.
15. A method for forming a portion of a semiconductor device structure comprising: providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate; forming a first isolation trench within the semiconductor active layer, depositing a stressor material on a bottom of the first isolation trench, wherein the stressor material includes a dual-use film; and forming a second isolation trench within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second isolation trench, and wherein the presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> channel orientation of the semiconductor-on-insulator substrate, wherein the portion of the semiconductor device structure includes first and second transistor structures with first and second active semiconductor regions within the semiconductor active layer, respectively, the first transistor structure including a controlled stress feature in a width direction of the first transistor structure.
16. The method of claim 15 , wherein the first transistor structure is a PFET and the second transistor structure is an NFET.
17. The method of claim 15 , wherein the controlled stress feature of the first transistor structure includes first and second stress modifier features for providing modification of stresses in the width direction of the first transistor structure.
18. The method of claim 17 , wherein the first stress modifier feature includes a dual-use film external to the active semiconductor region of the first transistor structure, the dual-use film further being disposed along a bottom of third and fourth trenches adjacent at least two side portions of the first active semiconductor region of the first transistor structure.
19. The method of claim 17 , wherein the second stress modifier feature includes at least one stress modifier and capacitive reduction feature internal to the active semiconductor region of the first transistor structure.
20. The method of claim 19 , further wherein the at least one stress modifier and capacitive reduction feature extends between a source region and a drain region of the active semiconductor region of the first transistor structure.
21. The method of claim 19 , wherein the second stress modifier feature further comprises a trench with an absence of a dual-use stressor and anti-reflective coating film on a bottom of the respective trench.
22. The method of claim 17 , wherein the first and second stress modifier features comprise a plurality of trenches including a trench fill material.
23. The method of claim 22 , wherein the trench fill material comprises a material selected according to a desired additional stress modification for a particular transistor application with respect to either a compressive or a tensile stress modification.
24. The method of claim 22 , wherein the trench fill material includes oxide for providing a compressive stress modification.
25. The method of claim 22 , wherein the trench fill material includes a nitride for providing a tensile stress modification.
26. The method of claim 22 , wherein an active semiconductor region of the first transistor structure further includes a notch disposed at an end of the first active semiconductor region, the notch spanning between a source region and a drain region of the first active semiconductor region.
27. The method of claim 17 , wherein the first active semiconductor region is bounded by the first stress modifier feature, further wherein the first stress modifier feature includes an isolation trench having a dual-use stressor and anti-reflective coating film on a bottom of the isolation trench.
28. The method of claim 17 , wherein the controlled stress feature of the first transistor structure further includes third stress modifier and capacitive reduction features, wherein the third stress modifier and capacitive reduction features provide a further modification of stresses in the width direction of first transistor structure, wherein the third stress modifier and capacitive reduction features are disposed at opposite ends along edges of the active semiconductor region extending in a channel direction of the first transistor structure.
29. The method of claim 17 , wherein the controlled stress feature of the first transistor structure further includes alternate stress modifier and capacitive reduction features, wherein the alternate stress modifier and capacitive reduction features provide a further modification of stresses in the width direction of the portion of the semiconductor device structure.
30. The method of claim 29 , wherein the alternate stress modifier and capacitive reduction features are disposed completely across the active semiconductor region extending in a channel direction.
31. The method of claim 30 , further comprising: coupling portions of the active semiconductor region that are separated by the stress modifier and capacitive reduction features using an overlying metallization or an overlying metal interconnect level.
32. The method of claim 29 , further wherein the alternate stress modifier and capacitive reduction feature comprises a trench with an absence of the dual-use stressor and anti-reflective coating film lining a bottom of the respective trench, further wherein a trench sidewall liner of the respective trench extends fully within the respective trench, from a top of the semiconductor active layer down to the underlying insulation layer.
33. The method of claim 15 , wherein the semiconductor active layer has a <110> crystal orientation.
34. The method of claim 33 , further comprising: providing a plurality of stress modifier and capacitive reduction features contained within portions of source/drain regions of the active semiconductor region alone, without extending across a channel region of the active semiconductor region.
35. The method of claim 34 , further wherein the plurality of stress modifier and capacitive reduction features are disposed parallel to and along a gate electrode of the first transistor structure, and wherein the plurality of stress modifier and capacitive reduction features provide a modification of stresses in the channel direction of the first transistor structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 29, 2004
October 2, 2007
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