Semiconductor memory device and method of making design change to semiconductor chip

1. A semiconductor chip, comprising: a main driver comprising a pMOSFET, an nMOSFET and an output node, wherein the pMOSFET has a first gate for receiving a first control signal and the nMOSFET has a second gate for receiving a second control signal; an output pad coupled to the output node; a first control signal line for transmitting the first control signal; a second control signal line for transmitting the second control signal; a first predriver for driving the first control signal line; a second predriver for driving the second control signal line; the first control signal line is arranged physically next to and physically in parallel with the second control signal line.

2. The semiconductor chip of claim 1 , wherein; the first control signal line and the second control signal line are arranged so that the first control signal line and the second control signal line have a capacitance of zero therebetween when the first control signal has a value equal to that of the second control signal.

3. The semiconductor chip of claim 1 , wherein each of the first control signal line and the second control signal line has a length longer than a distance between the output node and the output pad.

4. The semiconductor chip of claim 1 , further comprising: a main region; and a peripheral region; wherein the output pad and the main driver are positioned on the peripheral region and the first predriver and the second predriver are positioned on the main region.

5. The semiconductor chip of claim 1 , further comprising: a first ground line; and a second ground line; wherein the first control signal line is positioned between the first ground line and the second control signal line, the first ground line is physically next to the first control signal line, the second control signal line is positioned between the first control signal line and the second ground line, and the second ground line is physically next to the second control signal line.

6. The semiconductor chip of claim 1 , further comprising: a first buffer coupled between the first control signal line and the gate of the pMOSFET; and a second buffer coupled between the second control signal line and the gate of the nMOSFET.

7. The semiconductor chip of claim 1 , further comprising a predetermined layer; wherein the first control signal line and the second control signal line are formed on the predetermined layer.

8. The semiconductor chip of claim 7 , further comprising a plurality of line layers, wherein the line layer is an uppermost line layer.

9. A semiconductor memory device comprising the semiconductor chip of claim 1 .

10. The semiconductor memory device of claim 9 , comprising a memory array, wherein the first control signal line and the second control signal line extend over the memory array.

11. A method of making design change to a semiconductor chip comprising a main driver, an output pad, a first control signal line, a second control signal line, a first predriver and a second predriver; wherein a main driver comprises an output node, a pMOSFET and an nMOSFET comprises a first gate for receiving a first control signal, the nMOSFET comprises a second gate for receiving a second control signal, the output pad is coupled to the output node, the first control signal line transmits the first control signal, the second control signal line transmits the second control signal, the first predriver drives the first control signal line, the second predriver drives the second control signal line, comprising: preparing layouts of the semiconductor chip; and arranging the first control signal line physically next to and physically in parallel with the second control signal line.