In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of accessing memory, comprising: storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation by an evaluation circuit on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell by reducing a load on the bit line with the evaluation circuit.
2. The method of claim 1 wherein reducing a load on the bit line includes reducing a number of cells coupled to the bit line.
3. The method of claim 1 wherein preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell includes reducing an amount of time required to perform the operation on the cell.
4. The method of claim 3 wherein reducing an amount of time required to perform the operation on the cell includes reducing an amount of time that stress that may cause the value of the bit stored in the cell from changing state is placed on the cell.
5. The method of claim 3 wherein reducing an amount of time required to perform the operation on the cell includes performing the operation on the cell before the value of the bit stored in the cell exceeds a voltage that causes an inverter in the cell from changing the state of the bit, wherein the inverter is formed from a subset of transistors in the group of transistors.
6. An apparatus for accessing memory including a plurality of cells, a subset of which includes at least a first cell coupled to a first set of bit lines and at least a second cell coupled to a second set of bit lines, comprising: evaluation logic coupled to the subset of cells and adapted to perform a read operation on a selected cell in the subset of cells such that a value of a bit stored in the selected cell is prevented from changing state while performing the read operation on the selected cell by reducing a load on the bit line.
7. The apparatus of claim 6 wherein the evaluation logic is further adapted to reduce a load on the bit line by reducing the number of cells coupled on the bit line.
8. The apparatus of claim 6 wherein: the apparatus is further adapted to reduce an amount of time required to read data perform the read operation on the cell selected to be read.
9. The apparatus of claim 8 wherein the apparatus is further adapted to reduce an amount of time that stress that may cause the value of the bit stored in the cell from changing state is placed on the cell.
10. The apparatus of claim 8 wherein the apparatus is further adapted to read data from the cell selected to be read before the value of the bit stored in the cell exceeds a voltage that causes an inverter included in the cell from changing the state of the bit.
11. The apparatus of claim 10 wherein the apparatus is further adapted to affect the state of a global bit line so that the state of the global bit line tracks the value stored in the cell before said value exceeds a voltage that causes an inverter included in the cell from changing the state of the value.
12. A system for accessing memory, comprising: a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store a bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell ; and evaluation logic coupled to the memory and adapted to perform the read operation on each cell and prevent the value of the bit stored in the cell from changing state by reducing a load on the bit line while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell.
13. The system of claim 12 wherein the evaluation logic is adapted to reduce a load on the bit line by reducing a number of cells coupled on the bit line.
14. The system of claim 12 wherein the evaluation logic is further adapted to reduce an amount of time required to perform the operation on the cell.
15. The system of claim 14 wherein the evaluation logic is further adapted to reduce an amount of time that stress that may cause the value of the bit stored in the cell from changing state is placed on the cell.
16. The system of claim 14 wherein the evaluation logic is further adapted to perform the operation on the cell before the value of the bit stored in the cell exceeds a voltage that causes an inverter in the cell from changing the state of the bit, wherein the inverter is formed from a subset of transistors in the group of transistors.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 21, 2005
October 30, 2007
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