In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1 further comprising: receiving the interleaving instruction.
3. The method of claim 1 wherein each of the first stream and the second stream includes 16 bits of encoded data.
4. The method of claim 1 wherein the bit interleaving instruction is a single executed instruction.
6. The apparatus of claim 5 wherein each of the first stream and the second stream includes 16 bits of encoded data.
8. The system of claim 7 wherein each of the first stream and the second stream includes 16 bits of encoded data.
10. The computer readable medium of claim 9 providing further instructions causing the processor to perform operations comprising: receiving the interleaving instruction.
11. The computer readable medium of claim 9 wherein each of the first stream and the second stream includes 16 bits of encoded data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 4, 2004
October 30, 2007
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