A semiconductor device is composed of a heat sink, an IC chip mounted and fixed on a specific face of the heat sink, a lead frame electrically connected to the IC chip and a sealing mold resin package. One or more of the faces of the heat sink has a specific surface area.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a heat sink having a surface with a predetermined range of surface roughening; an IC chip mounted and fixed on a specific face of the heat sink; a lead frame provided at locations surrounding the IC chip and electrically connected to the IC chip; and a sealing mold resin package for enclosing the heat sink, the IC chip, and the lead frame, wherein: a portion of the heat sink is exposed to the outside of the mold resin package; a portion of the lead frame protrudes out from the mold resin package as outer leads having a surface with a different predetermined range of surface roughening; when a specific surface area is defined as a ratio of an actual area of uneven surface to an area of an imaginary flat surface, the specific surface area of a surface of the heat sink is set at a value in the range 1.13 to 1.32; and the specific surface area of the surface of the outer leads is set at a value in the range 1.05 to 1.20 to optimize heat sink adhesion strength, resin-burr formation, and outer-lead placement on an external substrate.
2. A semiconductor device according to claim 1 , wherein the heat sink has a protrusion that bites into the mold resin package.
3. A semiconductor device according to claim 1 , wherein the IC chip is attached and fixed on the heat sink through an adhesive made of a resin, sandwiching the adhesive in conjunction with the heat sink.
4. A semiconductor device according to claim 3 , wherein the adhesive is made of a resin of an epoxy group.
5. A semiconductor device according to claim 1 , wherein the mold resin package is made of a resin of an epoxy group.
6. A semiconductor device according to claim 1 , wherein at least one of the surfaces of the heat sink and outer leads comprises an electrically plated roughened surface.
7. A semiconductor device according to claim 1 , wherein at least one of the surfaces of the heat sink and outer leads comprises an abrasion roughened surface.
8. A semiconductor device according to claim 1 , wherein at least one of the surfaces of the heat sink and outer leads comprises a sand blasted roughened surface.
9. A semiconductor device according to claim 1 , wherein at least one of the surfaces of the heat sink and outer leads comprises a chemically etched roughened surface.
10. A semiconductor device according to claim 1 , wherein at least one of the surfaces of the heat sink and outer leads comprises a laser beam roughened surface.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 4, 2005
November 13, 2007
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