Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A sense amplifier for coupling with an asymmetric SRAM cell that provides faster access times when the asymmetric SRAM cell stores a first predetermined binary value, said sense amplifier comprised of: a first pair of cross coupled inverters across a bitline (BL) and a bitline bar (BLB); a second pair of cross coupled inverters operably coupled with the first pair of cross coupled inverters; a plurality of additional transistors forming a dummy column of cells that store a second predetermined binary value at all times wherein during a read operation of the SRAM cell one of the dummy cells will have its wordline asserted, said dummy column of cells operably coupled with the first pair of cross coupled inverters; and four inputs operably coupled with a subset of transistors of the sense amplifier wherein the inputs include the BL, the BLB that derive from the SRAM cell, a dummy bit line (D), and a dummy bitline bar (DB) that are input to the dummy cells such that D is input to the sense amplifier on the same side as BLB while DB is input to the sense amplifier on the same side as BL.
2. The sense amplifier of claim 1 wherein at least one of the transistors coupled with BL and BLB have higher transconductance characteristics than at least one of the transistors coupled with D and DB.
3. The sense amplifier of claim 1 wherein at least one of the transistors coupled with BL and BLB are selected from among the group consisting of: transistors having a lower voltage threshold (V t ) as compared to the voltage threshold (V t ) of the transistors coupled with D and DB; transistors having a increased channel width as compared to the channel width of the transistors coupled with D and DB; and transistors having a decreased channel length as compared to the channel length of the transistors coupled with D and DB.
4. A combination SRAM device and sense amplifier comprising: an array of SRAM cells wherein each SRAM cell stores a binary variable representing a predetermined binary value, and wherein each SRAM cell is an asymmetric SRAM cell having reduced leakage power with respect to a comparable symmetric SRAM cell, each asymmetric SRAM cell comprising: a plurality of transistors operably coupled and configured as an asymmetric SRAM cell, wherein the plurality of transistors include at least one of a first type of transistor and at least one of a second type of transistor that is weaker than the first type of transistor, such that the configuration of each asymmetric SRAM cell achieves reduced leakage power with respect to a symmetric SRAM cell having the first type of transistor only; and at least one sense amplifier comprised of: a first pair of cross coupled inverters across a bitline (BL) and a bitline bar (BLB); a second pair of cross coupled inverters operably coupled with the first pair of cross coupled inverters; a plurality of additional sense amplifier transistors forming a dummy column of cells that store a second predetermined binary value at all times wherein during a read operation of the SRAM cell one of the dummy cells will have its wordline asserted, said dummy column of cells operably coupled with the first pair of cross-coupled inverters; and four inputs operably coupled with a subset of the sense amplifier transistors wherein the inputs include the BL, the BLB that derive from the SRAM cell, a dummy bit line (D), and a dummy bitline bar (DB) that are input to the dummy cells such that D is input to the sense amplifier on the same side as BLB while DB is input to the sense amplifier on the same side as BL.
5. The combination SRAM device and sense amplifier of claim 4 wherein the sense amplifier transistors coupled with BL and BLB have higher transconductance characteristics than the sense amplifier transistors coupled with D and DB.
6. The combination SRAM device and sense amplifier of claim 4 wherein at least one of the sense amplifier transistors coupled with BL and BLB are selected from among the group consisting of: transistors having a lower voltage threshold (V t ) as compared to the voltage threshold (V t ) of the transistors coupled with D and DB; transistors having a increased channel width as compared to the channel width of the transistors coupled with D and DB; and transistors having a decreased channel length as compared to the channel length of the transistors coupled with D and DB.
7. The combination SRAM device and sense amplifier of claim 4 wherein the SRAM device comprises an SRAM device selected from the group consisting of a direct store SRAM device and a selectively inverted SRAM device.
8. The combination SRAM device and sense amplifier of claim 7 wherein the array of SRAM cells in the SRAM device comprises a cache memory selected from the group consisting of a direct store cache memory and a selectively inverted cache memory.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 8, 2003
December 11, 2007
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