The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators. A first embodiment of this invention includes a plurality of serially connected transition matrix multiplication circuits producing a plurality of output state matrices. A second embodiment of this invention combines a first stage having plurality of matrix multiplication circuits connected to a first multiplexer circuit which selects an state matrix or one of the matrix products with a serial chain of matrix generator circuits including second matrix multiplication circuit and a second multiplexer selecting either a first input or the output of the second matrix multiplication circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A pseudo noise generator comprising: a state matrix generator receiving a multi-bit state input matrix and a count signal and generating a multi-bit state matrix output; a plurality of serially connected transition matrix multiplication circuits of predetermined order n each having a first input receiving a matrix input, a second input receiving a corresponding stored matrix and an output producing a matrix product of said matrix input and said stored matrix, said first input of a first transition multiplication circuit receiving said multi-bit state matrix output of said state matrix generator and said first input of other transition multiplication circuits connected to said output of a prior transition matrix multiplication in said serial connection, thereby producing a plurality of output state matrices.
2. A pseudo noise generator comprising: a plurality of first matrix multiplication circuits each having a first input receiving an input state matrix S 0 , a second input receiving a corresponding stored matrix and an output producing a matrix product of said input state matrix S 0 and said stored matrix; a first multiplexer circuit having a plurality of matrix inputs, a first matrix input receiving said input state matrix S 0 and each other matrix input connected to said output of a corresponding one of said first matrix multiplication circuits, a control input and an output, said first multiplexer circuit connecting one matrix input to said matrix output corresponding to a control signal received at said control input; and a plurality of serially connected matrix generator circuits having a matrix input and a matrix output, said matrix input of a first matrix generator circuit connected to said matrix output of said first multiplexer circuit and said matrix input of other matrix generator circuit connected to said matrix output of a prior matrix generator in said serial connection, each matrix generator circuit including: a second matrix multiplication circuit having a first matrix input connected to said matrix input of said matrix generator circuit, a second matrix input receiving a corresponding stored matrix and an output producing a matrix product of said matrix input and said stored matrix, and a second multiplexer having a first input connected to said matrix input of said matrix generator circuit, a second input connected to said output of said corresponding second matrix multiplication circuit, a control input and an output connected to said matrix output of said matrix generating circuit, said second multiplexer connecting one matrix input to said matrix output corresponding to a control signal received at said control input.
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April 16, 2003
January 8, 2008
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