An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode, the apparatus comprising: an internal address generator for receiving an external bank address and generating internal bank addresses based on the external bank address in response to a compress test signal and a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of at least one bank selected by the internal bank addresses in response to an additive latency signal, the compress test signal and the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the selected banks, wherein, in the compress test mode, the plurality of banks are simultaneously activated or selectively activated in response to the bank interleaving test signal.
2. The apparatus as recited in claim 1 , wherein the internal bank addresses are classified into non-delay internal bank addresses and delay internal bank addresses.
3. The apparatus as recited in claim 2 , wherein the internal address generator includes: a latch controller for receiving the compress test signal and the bank interleaving test signal and controlling a latch control signal; a buffer block for converting the external bank address into the internal bank addresses; a latching block controlled by the latch control signal for latching the internal addresses to thereby output the internal addresses as the non-delay internal bank addresses; and a routing block for delaying the non-delay internal bank addresses outputted from the latching block to thereby generate the delay internal bank addresses.
4. The apparatus as recited in claim 3 , wherein the buffer block includes a plurality of buffers, each corresponding to each bit of the external bank address.
5. The apparatus as recited in claim 4 , wherein the latching block includes a plurality of latches, controlled by the latch control signal, each corresponding to each bit of the external bank address.
6. The apparatus as recited in claim 5 , wherein the routing block includes a plurality of routers, each corresponding to each bit of the external bank address.
7. The apparatus as recited in claim 2 , wherein the read operation block includes: a read decoding block for decoding one of the non-delay internal bank addresses and the delay internal bank addresses based on the additive latency signal, the compress test signal and the bank interleaving test signal to thereby generate a plurality of read bank operating signals; a compress controlling block controlled by a read activation signal for receiving the plurality of read bank operation signals and generating a plurality of strobe signals; and a data compress block for compressing a plurality of data outputted from cell arrays in the selected banks and generating a test result signal in response to the compress test signal and the plurality of strobe signals.
8. The apparatus as recited in claim 7 , wherein the read decoding block includes: a control signal generator for receiving the additive latency signal, the compress test signal and the bank interleaving test signal to thereby generate first and second control signals; and a plurality of decoders, each for decoding the non-delay internal bank addresses and the delay internal bank addresses in response to the first and second control signals, wherein each decoder corresponds to each of the plurality of banks.
9. The apparatus as recited in claim 8 , wherein the data compress block includes a plurality of DQ output buffers, each corresponding to each of the plurality of banks.
10. The apparatus as recited in claim 9 , wherein the DQ output buffer includes: a strobe control generator for generating an output control signal, first and second data strobe signals in response to a normal state information signal, the compress test signal and the strobe signals; a comparison block for receiving the plurality of data and generating the test result signal; a strobe driving block for outputting the test result signal in response to the first and second control signals; and an output controller for outputting the test result signal in response to the output control signal.
11. The apparatus as recited in claim 2 , wherein the write operating testing block includes: a write decoding block for decoding the non-delay internal bank addresses to thereby generate a plurality of write bank operating signals; a write controlling block controlled by a write activation signal for receiving the plurality of write bank operating signals and generating a plurality of write driving signals; and a data compress block for storing inputted data in cell arrays in the selected banks in response to the plurality of write driving signals.
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June 30, 2004
January 22, 2008
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