There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: (a) an interconnect substrate having first and second main surfaces on opposite sides; (b) a first semiconductor chip mounted on a side of the first main surface of said interconnect substrate and having a memory circuit; (c) a second semiconductor chip mounted on a side of the first main surface of said interconnect substrate and having a circuit controlling said memory circuit; and (d) a sealing body formed on a side of the first main surface of said interconnect substrate to seal the first and second semiconductor chips; wherein plural first terminals and plural second terminals are arranged on the first main surface of said interconnect substrate, plural terminals of said first semiconductor chip being electrically connected with the first terminals, plural terminals of said second semiconductor chip being electrically connected with the second terminals; wherein plural first external terminals and plural second external terminals are arranged on the second main surface of said interconnect substrate, the first external terminals being electrically connected with the second semiconductor chip via interconnects located inside said interconnect substrate, the second external terminals being electrically connected with plural interconnects located inside said interconnect substrate which electrically connect said first and second semiconductor chips; wherein said first external terminals are arranged in plural rows along an outer periphery of the second main surface of said interconnect substrate; wherein said second external terminals are arranged in an inner region located more inwardly than, and spaced from, the innermost row of the first external terminals by a distance equal to or greater than the spacing between adjacent rows of the first external terminals, and wherein said second semiconductor chip and said first semiconductor chip are stacked on top of each other.
2. A semiconductor device as set forth in claim 1 , wherein said second external terminals are coated with an insulating layer formed on a top-level layer of the second main surface of said interconnect substrate.
3. A semiconductor device as set forth in claim 2 , wherein said insulating layer is made of solder resist.
4. A semiconductor device as set forth in claim 1 , wherein said second external terminals are exposed from an insulating layer formed on a top-level layer of the second main surface of said interconnect substrate.
5. A semiconductor device as set forth in claim 1 , wherein said memory circuit is a synchronous DRAM.
6. A semiconductor device as set forth in claim 5 , wherein said synchronous DRAM is a DDR synchronous DRAM.
7. A semiconductor device as set forth in claim 1 , wherein solder bumps are connected with said first external terminals.
8. A semiconductor device as set forth in claim 1 , wherein solder bumps are connected with said first external terminals, and wherein no solder bumps are connected with said second external terminals.
9. A semiconductor device as set forth in claim 1 , wherein said second semiconductor chip is mounted on the first main surface of said interconnect substrate such that plural terminals of said second semiconductor chip are electrically connected with said second terminals of the first main surface of said interconnect substrate via plural solder bumps, wherein said first semiconductor chip is laminated on said second semiconductor chip, and wherein plural terminals of said first semiconductor chip are electrically connected with said first terminals of the first main surface of said interconnect substrate via plural bonding wires.
10. A semiconductor device comprising: (a) an interconnect substrate having first and second main surfaces on opposite sides; (b) a first semiconductor chip mounted on a side of the first main surface of said interconnect substrate and having a memory circuit; (c) a second semiconductor chip mounted on a side of the first main surface of said interconnect substrate and having a circuit controlling said memory circuit; and (d) a sealing body formed on a side of the first main surface of said interconnect substrate to seal the first and second semiconductor chips; wherein plural first terminals and plural second terminals are arranged on the first main surface of said interconnect substrate, plural terminals of said first semiconductor chip being electrically connected with the first terminals, plural terminals of said second semiconductor chip being electrically connected with the second terminals; wherein plural first external terminals and plural second external terminals are arranged on the second main surface of said interconnect substrate, the first external terminals being electrically connected with the second semiconductor chip via interconnects located inside said interconnect substrate, the second external terminals being electrically connected with plural interconnects located inside said interconnect substrate which electrically connect said first and second semiconductor chips; wherein said first external terminals are arranged in plural rows extending inward from an outer periphery of the second main surface of said interconnect substrate; wherein said second external terminals are arranged in an inner region which is located more inwardly than, and spaced from, the innermost row of the first external terminals by a distance equal to or greater than the spacing between adjacent rows of the first external terminals; wherein the plural interconnects located inside said interconnect substrate and electrically connecting said first and second semiconductor chips are data lines electrically connecting the memory circuit of said first semiconductor chip and the circuit which is located inside the second semiconductor chip and controls said memory circuit, and wherein said second semiconductor chip and said first semiconductor chip are stacked on top of each other.
11. A semiconductor device as set forth in claim 10 , wherein said second external terminals are coated with an insulating layer formed in a top-level layer of the second main surface of said interconnect substrate.
12. A semiconductor device as set forth in claim 11 , wherein said insulating layer is made of solder resist.
13. A semiconductor device as set forth in claim 10 , wherein said second external terminals are exposed from an insulating layer formed in a top-level layer of the second main surface of said interconnect substrate.
14. A semiconductor device as set forth in claim 10 , wherein said memory circuit is a synchronous DRAM.
15. A semiconductor device as set forth in claim 14 , wherein said synchronous DRAM is a DDR synchronous DRAM.
16. A semiconductor device as set forth in claim 10 , wherein solder bumps are connected with said first external terminals.
17. A semiconductor device as set forth in claim 10 , wherein solder bumps are connected with said first external terminals, and wherein no solder bumps are connected with said second external terminals.
18. A semiconductor device as set forth in claim 10 , wherein said second external terminals are located more inwardly than planar regions of said first and second semiconductor chips.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 9, 2005
January 29, 2008
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