According to some embodiments, a Single-Instruction/Multiple-Data averaging operation is presented. The averaging operation averages multiple sets of data elements, for example, two data elements each from a first source and a second source, producing a set of averages. In at least one embodiment, in a first adder stage, a first plurality of data elements are added to a second plurality of data elements, generating a plurality of intermediate results. In a second adder stage, multiple different combinations of the plurality of intermediate results are added together, generating a plurality of sum results. The two least significant bits of each sum result are discarded.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a plurality of first adders, each first adder of the plurality of first adders operative to add two operands of a plurality of operands into one of a plurality of intermediate results; a plurality of second adders, each second adder of the plurality of second adders operative to add two intermediate results of the plurality of intermediate results into one of a plurality of sum results; and discard circuitry operative to discard the two least significant bits of each sum result of the plurality of sum results.
2. The apparatus as recited in claim 1 , wherein the plurality of first adders comprises eight first adders and the plurality of second adders comprises seven second adders.
3. The apparatus as recited in claim 1 , wherein the discard circuitry comprises a plurality of shift registers.
4. The apparatus as recited in claim 1 , wherein each of the first adders are operative to add two eight-bit input operands producing a nine-bit intermediate operand and each of the second adders are operative to add two nine-bit intermediate operands producing a ten-bit output operand.
5. The apparatus as recited in claim 1 , wherein each of the first adders are operative to add two sixteen-bit input operands producing a seventeen-bit intermediate operand and each of the second adders are operative to add two seventeen-bit intermediate operands producing an eighteen-bit operand.
6. The apparatus as recited in claim 1 , wherein routing of the plurality of operands and the plurality of intermediate results to the plurality of first adders and the plurality of second adders is selected according to microcode identified by a Single-Instruction/Multiple-Data (SIMD) instruction.
7. The apparatus as recited in claim 1 , wherein routing of the plurality of operands and the plurality of intermediate results to the plurality of first adders and the plurality of second adders is selected according to decode logic and a Single-Instruction/Multiple-Data (SIMD) instruction.
8. The apparatus as recited in claim 1 , wherein the plurality of first adders, the plurality of second adders, and the discard circuitry form a Single-Instruction/Multiple-Data (SIMD) instruction execution circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 26, 2004
February 5, 2008
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