System and method for memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a new cache line-sized memory request, determining whether a number of pending requests is less than a fetch limit that is equal to or less than a number of cache lines of a cache memory; and responsive to a determination that the number of pending requests is less than the fetch limit, performing an arbitration among all of the pending requests, including the new cache line-sized memory request.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory utilization method in a computer system, the method comprising: receiving requests from a plurality of entities, wherein the requests are cache line-sized memory requests; determining whether a number of pending requests is less than a fetch limit that is equal to a number of cache lines of a cache memory; responsive to a determination that the number of pending requests is less than the fetch limit, performing an arbitration among all of the received requests; and processing the received request that wins the arbitration.
2. The method of claim 1 further comprising, responsive to a determination that the number of pending requests is greater than or equal to the fetch limit, waiting until the number of pending requests falls below the fetch limit.
3. The method of claim 1 wherein the cache memory is an input/output (“I/O”) cache memory.
4. The method of claim 1 wherein the cache memory is a coherent cache memory.
5. The method of claim 1 wherein the requests comprise a portion of a DMA read request from an I/O device.
6. The method of claim 1 wherein the requests comprise a portion of a DMA write request from an I/O device.
7. A memory utilization method in a computer system, the method comprising: receiving DMA transactions from a plurality of entities; dividing the DMA transactions into a number of new cache line-sized memory requests; determining whether a number of pending memory requests is less than the total number of cache lines of a cache memory; responsive to, a determination that the number of pending memory requests is less than the total number of cache lines of the cache memory, performing an arbitration among the new cache line-sized memory requests; and responsive to completing the arbitration, issuing one of the new cache line-sized memory requests that wins the arbitration.
8. The method of claim 7 further comprising, responsive to a determination that the number of pending memory requests Is not less than the total number of cache lines of the cache memory, waiting until the number of pending memory requests falls below the total number of cache lines of the cache memory.
9. The method of claim 7 wherein the cache memory is an input/output (“I/O”) cache memory.
10. The method of claim 7 wherein the cache memory is a coherent cache memory.
11. The method of claim 7 wherein the DMA transactions comprise a DMA read request.
12. The method of claim 7 wherein the DMA transactions comprise a DMA write request.
13. A system for performing DMA transactions in a computer, the system comprising: cache means for storing data in connection with DMA transactions; means for receiving requests from a plurality of entities, wherein the requests are cache line-sized memory requests; means for determining whether a number of pending requests is less than a fetch limit, wherein the fetch limit is equal to a number of lines of the cache means; means responsive to a determination that the number of pending requests is less than the fetch limit for performing an arbitration among all of the received requests; and means for processing the received request that wins the arbitration.
14. The system of claim 13 further comprising means responsive to a determination that the number of pending requests is not less than the fetch limit for waiting until the number of pending requests falls below the fetch limit.
15. The system of claim 13 wherein the cache means is an input/output (“I/O”) cache memory.
16. The system of claim 13 wherein the cache means is a coherent cache memory.
17. The system of claim 13 wherein the requests comprise a portion of a DMA read request from an I/O device.
18. The system of claim 13 wherein the requests comprise a portion of a DMA write request from an I/O device.
19. A memory utilization system in a computer, the system comprising: means for receiving DMA transactions from a plurality of entities; means for dividing DMA transactions into a number of new cache line-sized memory requests; means for determining whether a number of pending memory requests is less than the total number of cache lines of a cache memory; means responsive to a determination that the number of pending memory requests is less than the total number of cache lines of the cache memory for performing an arbitration among the new cache line-sized memory requests; and means for issuing the memory request that wins the arbitration.
20. The system of claim 19 further comprising means responsive to a determination that the number of pending memory requests is not less than the total number of cache lines of the cache memory for waiting until the number of pending memory requests falls below the total number of cache lines of the cache memory.
21. The system of claim 19 wherein the cache memory is an input/output (“I/O”) cache memory.
22. The system of claim 19 wherein the cache memory is a coherent cache memory.
23. A computer-readable medium operable with a computer for performing DMA transactions in a computer, the medium having stored thereon: instructions executable by the computer for receiving requests from a plurality of entities; instructions executable by the computer for determining whether a number of pending requests is less than a fetch limit, wherein the fetch limit is equal to a number of lines of a cache means; instructions executable by the computer responsive to a determination that the number of pending requests is less than the fetch limit for performing an arbitration among all of the received requests; and instructions executable by the computer for processing the received request that wins the arbitration.
24. The medium of claim 23 further having stored thereon instructions executable by the computer responsive to a determination that the number of pending requests is not less than the fetch limit for waiting until the number of pending requests falls below the fetch limit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 2, 2005
February 5, 2008
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