A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memory signals to and from a tester through a memory bus. The test interface circuit couples test signals to the memory hub in the memory module through a communications link responsive to command, address and data signals received from the tester. The test interface circuit also receives signals from the memory hub in the memory module through the communications link that are indicative of the response of the memory module to the test signals. The test interface circuit then provides corresponding results data to the tester.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system for testing at least one memory module having a memory hub coupled to a communications link and a plurality of memory devices coupled to the memory hub, the system comprising: a tester coupled having a memory bus, the tester being operable to transfer memory signals to and from the memory bus; and a test interface circuit having a memory interface coupled to the tester through the memory bus, the test interface circuit being coupled to the at least one memory module through the communications link, the test interface circuit being operable to couple test signals to the memory hub in the memory module through the communications link responsive to command, address and data signals received from the tester, the test interface circuit further being operable to receive signals from the memory hub in the memory module through the communications link indicative of the response of the memory module to the test signals and to provide corresponding results data to the tester, wherein the test interface circuit comprises: a memory interface coupled to the tester through a data bus and at least one command and address bus; a cyclic redundancy generator coupled to receive signals from the memory interface and operable to generate error checking code signals corresponding thereto; a frame builder circuit coupled to receive the signals from the memory interface and the error checking code signals from the cyclic redundancy generator and to convert the signals to a write signal packet; and a frame transmitter coupled to receive the write signal packet from the frame builder, the frame transmitter being operable to transmit the write signal packet to the at least one memory module through the communications link.
2. The system of claim 1 wherein the test interface circuit comprises circuitry that is substantially identical to circuitry in the memory hub in the at least one memory module.
3. The system of claim 2 wherein the test interface circuit comprises circuitry that is identical to circuitry in the memory hub in the at least one memory module.
4. The system of claim 1 wherein the test interface circuit is operable to convert a read data packet received from the at least one memory module through the communications link to read data signals, the tester being coupled to receive the read data signals from the test interface circuit responsive to command and address signals applied by the tester to the test interface circuit.
5. The system of claim 1 wherein the test interface circuit is coupled to receive command, address and write data signals from the tester and to convert the command, address and write data signals to a write data packet, the test interface circuit being operable to apply the write data packet to the at least one memory module through the communications link.
6. The system of claim 1 wherein the test interface circuit further comprises: a cyclic redundancy checker coupled to the at least one memory module through the communications link, the cyclic redundancy checker being operable to receive a read data packet from the at least one memory module containing read data signals and error checking code signals and to determine if the read data signals correspond to the error checking code signals; and a frame decomposer coupled to receive the read data packet and to apply signals corresponding to the read data packet to the memory interface.
7. The system of claim 1 wherein the communications link comprises: a high-speed downstream bus coupling signals from the test interface circuit to the at least one memory module; and a high-speed upstream bus coupling signals from the at least one memory module to the test interface circuit.
8. The system of claim 7 wherein the high-speed upstream bus has a width that is greater than the width of the high-speed downstream bus.
9. The system of claim 1 wherein the memory bus comprises a bi-directional data bus and a bi-directional command/address bus.
10. A system for testing at least one memory module having a memory hub coupled to a communications link and a plurality of memory devices coupled to the memory hub, the system comprising: a tester coupled having a memory bus, the tester being operable to transfer memory signals to and from the memory bus; and a test interface circuit having a memory interface coupled to the tester through the memory bus, the test interface circuit being coupled to the at least one memory module through the communications link, the test interface circuit being operable to couple test signals to the memory hub in the memory module through the communications link responsive to command, address and data signals received from the tester, the test interface circuit further being operable to receive signals from the memory hub in the memory module through the communications link indicative of the response of the memory module to the test signals and to provide corresponding results data to the tester, wherein the test interface circuit comprises: a cyclic redundancy checker coupled to the at least one memory module through the communications link, the cyclic redundancy checker being operable to receive a read data packet from the at least one memory module containing read data signals and error checking code signals and to determine if the read data signals correspond to the error checking code signals; and a frame decomposer coupled to receive the read data packet and to apply signals corresponding to the read data packet to the memory interface.
11. The system of claim 10 wherein the test interface circuit comprises circuitry that is substantially identical to circuitry in the memory hub in the at least one memory module.
12. The system of claim 11 wherein the test interface circuit comprises circuitry that is identical to circuitry in the memory hub in the at least one memory module.
13. The system of claim 10 wherein the test interface circuit is operable to convert a read data packet received from the at least one memory module through the communications link to read data signals, the tester being coupled to receive the read data signals from the test interface circuit responsive to command and address signals applied by the tester to the test interface circuit.
14. The system of claim 10 wherein the test interface circuit is coupled to receive command, address and write data signals from the tester and to convert the command, address and write data signals to a write data packet, the test interface circuit being operable to apply the write data packet to the at least one memory module through the communications link.
15. The system of claim 10 wherein the communications link comprises: a high-speed downstream bus coupling signals from the test interface circuit to the at least one memory module; and a high-speed upstream bus coupling signals from the at least one memory module to the test interface circuit.
16. The system of claim 15 wherein the high-speed upstream bus has a width that is greater than the width of the high-speed downstream bus.
17. The system of claim 10 wherein the memory bus comprises a bi-directional data bus and a bi-directional command/address bus.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 1, 2005
February 5, 2008
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