A system and method is disclosed for providing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of the integrated circuit. In one advantageous embodiment the radiation resistant material is silicon carbide. In another advantageous embodiment a passivation layer is placed between the device active area and the layer of radiation resistant material. The integrated circuit of the present invention exhibits minimal sensitivity to (1) enhanced low dose rate sensitivity (ELDRS) effects of radiation, and (2) pre-irradiation elevated temperature stress (PETS) effects of radiation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing an integrated circuit, comprising the steps of: providing a device active area of an integrated circuit and a first metal layer; and applying a layer of radiation resistant material directly on said device active area of said integrated circuit and said first metal layer, the layer of radiation resistant material operable to protect the device active area from radiation in space.
2. The method as set forth in claim 1 , further comprising the step of: applying a layer of plastic material to said layer of radiation resistant material.
3. The method as set forth in claim 1 wherein said layer of radiation resistant material comprises a layer of silicon carbide.
4. The method as set forth in claim 3 further comprising the step of: applying a layer of plastic material to said layer of silicon carbide.
5. The method of claim 1 , wherein the device active area comprises a bipolar linear integrated circuit.
6. The method of claim 1 , wherein the layer of radiation resistant material is operable to protect the device active area from effects due to electrons, gamma rays, heavy ions, protons, and neutrons.
7. A method for manufacturing an integrated circuit, comprising the steps of: providing a device active area of an integrated circuit and a first metal layer; and applying directly on said device active area of said integrated circuit and said first metal layer a layer of material operable to reduce sensitivity of said device active area of said integrated circuit to enhanced low dose rate sensitivity (ELDRS) effects of radiation in space.
8. The method as set forth in claim 7 wherein said layer of material that reduces sensitivity of said integrated circuit to enhanced low dose rate sensitivity (ELDRS) effects of radiation comprises a layer of silicon carbide.
9. The method as set forth in claim 8 further comprising the step of: applying a layer of plastic material to said layer of material that reduces sensitivity of said integrated circuit to enhanced low dose rate sensitivity (ELDRS) effects of radiation.
10. The method of claim 7 , wherein the device active area comprises a bipolar linear integrated circuit.
11. The method of claim 7 , wherein the ELDRS effects of radiation comprise effects due to electrons, gamma rays, heavy ions, protons, and neutrons.
12. A method for manufacturing an integrated circuit, comprising the steps of: providing a device active area of an integrated circuit and a first metal layer; and applying directly on said device active area of said integrated circuit and said first metal layer a layer of material operable to reduce sensitivity of said device active area of said integrated circuit to said pre-irradiation elevated temperature stress (PETS) effects of radiation in space.
13. The method as set forth in claim 12 wherein said layer of material that reduces sensitivity of said integrated circuit to said pre-irradiation elevated temperature stress (PETS) effects of radiation comprises a layer of silicon carbide.
14. The method as set forth in claim 12 further comprising the step of: applying a layer of plastic material to said layer of material that reduces sensitivity of said integrated circuit to said pre-irradiation elevated temperature stress (PETS) effects of radiation.
15. The method of claim 12 , wherein the device active area comprises a bipolar linear integrated circuit.
16. The method of claim 12 , wherein the PETS effects of radiation comprise effects due to electrons, gamma rays, heavy ions, protons, and neutrons.
17. An integrated circuit, comprising: a device active area of said integrated circuit; a first metal layer; and a layer of radiation resistant material applied directly on said device active area of said integrated circuit and said first metal layer, the layer of radiation resistant material operable to protect the device active area from radiation in space.
18. The integrated circuit as set forth in claim 17 wherein said layer of radiation resistant material comprises a layer of silicon carbide.
19. The integrated circuit as set forth in claim 18 further comprising a layer of plastic material applied to said layer of silicon carbide.
20. The integrated circuit of claim 17 , wherein the device active area comprises a bipolar linear integrated circuit.
21. The integrated circuit of claim 17 , wherein the layer of radiation resistant material is operable to protect the device active area from effects due to electrons, gamma rays, heavy ions, protons, and neutrons.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 8, 2004
February 12, 2008
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