A power control circuit is presented. The circuit includes a pair of parallel optocoupler/logic stages and a pair of parallel voltage-to-current driver stages electrically coupled to a halfbridge stage in the order described. An input signal is communicated to the optocoupler/logic stage and processed therein to produce two distinctly separate but complimentary waveforms. Complimentary waveforms are communicated to the voltage-to-current driver stage to drive a paired arrangement of JFET switches. Thereafter, the JFET switches communicate with the halfbridge stage to control function of BJT switches. BJT switches are sequenced to produce a high power output. The present invention has immediate applicability to power conditioning, control, and distribution systems, as well as other applications which include or rely on silicon power transistors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A power control circuit comprising: (a) a first optocoupler/logic stage, said first optocoupler/logic stage receiving a first input signal and outputting a first pair of complimentary voltage waveforms; (b) a second optocoupler/logic stage, said second optocoupler/logic stage receiving a second input signal and outputting a second pair of complimentary voltage waveforms; (c) a first voltage-to-current driver stage, said first optocoupler/logic stage electrically coupled to said first voltage-to-current driver stage, said first pair of complimentary voltage waveforms driving to a first pair of JFET switches within said first voltage-to-current driver stage; (d) a second voltage-to-current driver stage, said second optocoupler/logic stage electrically coupled to said second voltage-to-current driver stage, said second pair of complimentary voltage waveforms driving to a second pair of JFET switches within said second voltage-to-current driver stage; and (e) a halfbridge stage, said first voltage-to-current driver stage and said second voltage-to-current driver stage electrically coupled to said halfbridge stage, said first pair of JFET switches controlling a first BJT switch within said halfbridge stage, said second pair of JFET switches controlling a second BJT switch within said halfbridge stage, said first BJT switch and said second BJT switch functionally sequenced to produce a high-power output signal.
2. The power control circuit of claim 1 , wherein said first pair of JFET switches and said second pair of JFET switches are composed of a temperature resistant silicon carbide.
3. The power control circuit of claim 1 , wherein said first BJT switch and said second BJT switch are composed of a temperature resistant silicon carbide.
4. The power control circuit of claim 1 , wherein said first optocoupler/logic stage and said second optocoupler/logic stage each comprising: (i) an optocoupler; (ii) a first comparator electrically coupled to said optocoupler; (iii) a pair of rise time delay circuits each having a diode and a resistor electrically coupled and parallel, each said rise time delay circuit electrically coupled at one end to said first comparator; (iv) a second comparator electrically coupled to one said rise time delay circuit, said second comparator electrically coupled to one said JFET switch within said first voltage-to-current driver stage; (v) a third comparator electrically coupled to another said rise time delay circuit, said third comparator electrically coupled to another said JFET switch within said first voltage-to-current driver stage, said second comparator electrically coupled to said third comparator; (vi) a trimmer circuit electrically coupled between said second comparator and said third comparator, said trimmer circuit eliminating cross conduction between said JFET switches; and (vii) a pair of variable capacitors, one said variable capacitor electrically coupled at one end between one said rise time delay circuit and said second comparator and grounded at another end, another said variable capacitor electrically coupled at one end between another said rise time delay circuit and said third comparator and grounded at another end.
5. The power control circuit of claim 4 , wherein said trimmer circuit comprising: (viii) a variable resistor grounded at one end and attached to a power source at another end.
6. The power control circuit of claim 1 , wherein said first voltage-to-current driver stage and said second voltage-to-current driver stage each comprising: (i) a pair of JFET switches electrically coupled in series, said pair of JFET switches electrically coupled at one end to a power source and at another to said halfbridge stage; and (ii) a rise time delay circuit having a diode and a resistor electrically coupled and parallel, said rise time delay circuit electrically coupled at one end between said pair of JFET switches and at another end to one said BJT switch.
7. The power control circuit of claim 1 , wherein said halfbridge stage comprising: (i) a first BJT switch electrically coupled and parallel to a first diode, said first BJT switch and said first diode electrically coupled at one end to a power supply; and (ii) a second BJT switch electrically coupled and parallel to a second diode, said second BJT switch and said second diode electrically coupled at one end to ground and at another end to said first BJT switch and said first diode.
8. The power control circuit of claim 7 , further comprising: (iii) an electrical lead electrically coupled at one end between said first BJT switch and said second BJT switch.
9. The power control circuit as in one of claims 1 - 8 , wherein said power control circuit is disposed along a thermally conductive substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 26, 2005
February 12, 2008
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