A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the address/command word. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. Read data is read from the array or is received from a second data bus port for subsequent re-driving on the first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory chip comprising: a first input configured to receive an address/command word; a first output configured to re-drive an address/command word; circuitry configured to determine from contents of the address/command word if the address/command word is directed to the memory chip; and an array capable of storing data; wherein the memory chip is configured to make a read from or write to the array when the address/command word is determined to be directed to the memory chip; if the address/command word is determined to not be directed to the memory chip, the memory chip is configured to re-drive the address/command word onto the first output.
2. The memory chip of claim 1 further comprising: a second input configured to receive a bus clock, the bus clock used by the memory chip to receive the address/command word and to re-drive the address/command word; and a second output configured to re-drive the bus clock.
3. The memory chip of claim 2 , further comprising a phase locked loop circuit configured to convert a first frequency of the bus clock into a second frequency, the second frequency used to receive the address/command word and to re-drive the address/command word.
4. The memory chip of claim 2 further comprising: a third input, configured to receive timing signals, the timing signals used to time access of the array; and a third output, configured to re-drive the timing signals.
5. The memory chip of claim 4 further comprising a first data bus port configured to receive a first data word.
6. The memory chip of claim 5 further comprising a second data bus port configured to re-drive the first data word.
7. The memory chip of claim 6 , the second data bus port further configured to receive a second data word.
8. The memory chip of claim 7 , the first data bus port further configured to re-drive the second data word.
9. The memory chip of claim 8 in which all I/Os in the first data bus port are configured to be bidirectional I/Os.
10. The memory chip of claim 9 in which all I/Os in the second data bus port are configured to be bidirectional I/Os.
11. The memory chip of claim 8 in which a first portion of I/Os in the first data bus port are configured to be receivers and a second portion of I/Os in the first data bus port are configured to be drivers.
12. The memory chip of claim 10 in which a first portion of I/Os in the second data bus port are configured to be receivers and a second portion of I/Os in the second data bus port are configured to be drivers.
13. The memory chip of claim 8 , further comprising: a first read queue to store data read from the array; and a first write queue to store data to be written to the array.
14. The memory of claim 12 wherein the memory chip is configured to associate an address/command word received with data received from the first data bus port.
15. The memory chip of claim 8 , further comprising: a second read queue to store data received from the second data bus port; and a second write queue to store data to be re-driven to the second data bus port.
16. The memory chip of claim 14 wherein the memory chip is configured to select data from the first read queue or data from the second read queue and drive the selected data onto the first data bus port.
17. The memory chip of claim 14 wherein the memory chip is configured to re-drive data from the second write queue onto the second data bus port.
18. The memory chip of claim 1 wherein the first input receives a single bit of data at a time; wherein the address/command word comprises a chip ID field in a leading position; the memory chip configured to check if a first bit in the chip ID field has a first logical value; if so, the memory chip is configured to store the address/command work on the memory chip; if the first bit in the chip ID field has a second logical value, the memory chip is configured to re-drive the address/command word on the first output with the chip ID field shifted by one bit, with the first bit in the chip ID field being discarded, and a second bit in the chip ID field becoming a new first bit in the chip ID field.
19. The memory chip of claim 17 wherein the address/command word re-drive onto the first output begins one cycle of transmission of the first input after the first bit in the chip ID field is received from the first input if the first bit in the chip ID field is the second logical value.
20. The memory chip of claim 1 , wherein the address/command word contains data to be written to the array if the address/command word is determined to be directed to the memory chip.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 26, 2006
March 11, 2008
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