Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a first memory transistor; and a peripheral circuit transistor, wherein the first memory transistor comprises: a semiconductor layer; a first insulating film formed on a memory cell region of the semiconductor layer; a first electrode layer formed on the first insulating film; a first element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the first element isolating insulating film being self-aligned with the first electrode layer, a top face of the first element isolating insulating film being lower than a top face of the first electrode layer in a section perpendicular to a direction in which the first electrode layer extends; a second insulating film formed on the first electrode layer and the first element isolating insulating film; and a second electrode layer formed on the second insulating film, and the peripheral circuit transistor comprises: a third insulating film formed on a peripheral circuit region of the semiconductor layer; a third electrode layer formed on the third insulating film; a second element isolating insulating film; a fourth insulating film formed on the third electrode layer, the fourth insulating film including a first open portion exposing a surface of the third electrode layer; and a fourth electrode layer formed above the fourth insulating film and on the exposed surface of the third electrode layer, the fourth electrode layer being electrically connected to the third electrode layer via the first open portion.
2. The semiconductor device according to claim 1 , wherein a bottom face of the first electrode layer is lower than the top face of the first element isolating insulating film in the section.
3. The semiconductor device according to claim 1 , wherein a width of an upper portion of the first electrode layer is wider than a width of a lower portion of the first electrode layer.
4. The semiconductor device according to claim 1 , wherein: the second insulating film is formed continuously on the top face and side faces of the first electrode layer and the top face of the first element isolating insulating film; the second insulating film has a first portion formed on the top face of the first element isolating insulating film and a second portion formed on the top face of the first electrode layer; and the first portion is located below the second portion.
5. The semiconductor device according to claim 4 , wherein the first portion of the second insulating film is located above a top face of the first insulating film.
6. The semiconductor device according to claim 1 , wherein a bottom face of the second electrode layer above the first element isolating insulating film is lower than a bottom face of the second electrode layer above the first electrode layer.
7. The semiconductor device according to claim 1 , wherein a top face of the second element isolating insulating film is lower than a top face of the third electrode layer in a section perpendicular to a direction in which the third electrode layer extends.
8. The semiconductor device according to claim 1 , wherein: the first memory transistor further comprises a fifth electrode layer formed on the second insulating film; and the peripheral circuit transistor further comprises a sixth electrode layer formed on the fourth insulating film.
9. The semiconductor device according to claim 1 , wherein a plurality of transistors comprise at least two numbers of the peripheral circuit transistors, the first open portions of the peripheral circuit transistors having substantially equal widths.
10. The semiconductor device according to claim 1 , further comprising a first selective transistor, wherein the first selective transistor comprises: a fifth insulating film formed on the selective gate region of the semiconductor layer; a fifth electrode layer formed on the fifth insulating film; a third element isolating insulating film formed to extend through the fifth electrode layer and the fifth insulating film to reach the inner region of the semiconductor layer, the third element isolating insulating film being self-aligned with the fifth electrode layer; a sixth insulating film formed on the fifth electrode layer and the third element isolating insulating film, the sixth insulating film including a second open portion exposing a surface of the fifth electrode layer; a sixth electrode layer formed above the sixth insulating film and on the exposed surface of the fifth electrode layer, the sixth electrode layer being electrically connected to the fifth electrode layer via the second open portion.
11. The semiconductor device according to claim 10 , wherein: a gate length of the first selective transistor is longer than a gate length of the first memory transistor; and a gate length of the peripheral circuit transistor is longer than the gate length of the first selective transistor.
12. The semiconductor device according to claim 10 , wherein: the semiconductor device is a NAND type flash memory; the first selective transistor has first and second end portions in a direction of a gate length that is substantially perpendicular to a direction in which the sixth electrode layer extends; the first memory transistor is disposed on a side of the first end portion of the first selective transistor; and the semiconductor device further comprises: a second selective transistor having a structure equivalent to that of the first selective transistor, disposed on a side of the second end portion of the first selective transistor, and the sixth electrode layers of the first and second selective transistors being substantially parallel to each other; and a second memory transistor disposed on a side of the second selective transistor that is opposite to a side where the first selective transistor is disposed, and having a structure equivalent to that of the first memory transistor.
13. The semiconductor device according to claim 1 , wherein the second and fourth insulating films are insulating films including N.
14. The semiconductor device according to claim 1 , wherein the first memory transistor further comprises a fifth electrode layer formed on the second electrode layer.
15. The semiconductor device according to claim 1 , wherein the semiconductor device is a NAND type flash memory.
16. The semiconductor device according to claim 10 , wherein the third element isolating insulating film is located under the second open portion and has a groove having a shape which is the same as a shape of the second open portion.
17. The semiconductor device according to claim 10 , wherein a bottom face of the sixth electrode layer in the second open portion is located above a top face of the fifth insulating film.
18. The semiconductor device according to claim 10 , wherein the second open portion extends in a direction perpendicular to a direction of a gate length of the first selective transistor across the third element isolating insulating film.
19. The semiconductor device according to claim 1 , wherein: the first open portion has a first width in a direction of a gate length of the peripheral circuit transistor and a second width in a direction perpendicular to the direction of the gate length; and the second width is greater than the first width.
20. The semiconductor device according to claim 1 , wherein the first open portion is located at a center portion of the third electrode layer.
21. A semiconductor device comprising: a first memory transistor; and a peripheral circuit transistor, wherein the first memory transistor comprises: a semiconductor layer; a first insulating film formed on a memory cell region of the semiconductor layer; a first electrode layer formed on the first insulating film; a second electrode layer formed on the first electrode layer; a first element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the first element isolating insulating film being self-aligned with the first electrode layer, a top face of the first element isolating insulating film being lower than a top face of the second electrode layer in a section perpendicular to a direction in which the first electrode layer extends; a second insulating film formed on the second electrode layer and the first element isolating insulating film; and a third electrode layer formed on the second insulating film, and the peripheral circuit transistor comprises: a third insulating film formed on a peripheral circuit region of the semiconductor layer; a fourth electrode layer formed on the third insulating film; a second element isolating insulating film; a fourth insulating film formed on the fourth electrode layer, the fourth insulating film including a first open portion exposing a surface of the fourth electrode layer; and a fifth electrode layer formed above the fourth insulating film and on the exposed surface of the fourth electrode layer, the fifth electrode layer being electrically connected to the fourth electrode layer via the first open portion.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 16, 2007
April 1, 2008
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