The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for programming an array of memory cells arranged in rows and columns in a system having a capacitive coupling effect between adjacent memory cells, each memory cell having a first threshold voltage distribution window and a first programming step voltage that do not take into account the capacitive coupling effect, the method comprising: generating programming pulses to a first memory cell such that a coupling effect from adjacent memory cells is taken into account, the programming pulses comprising a series of programming voltages, each programming voltage in the series increased by a second programming step voltage from a previous programming voltage such that the first memory cell is in a second threshold voltage distribution window determined in response to the capacitive coupling effect, the second programming step voltage greater than the first programming step voltage and the second threshold voltage distribution window greater than the first threshold voltage distribution window.
2. The method of claim 1 wherein the first programming step voltage is 100 mV and the second programming step voltage is greater than 100 mV.
3. The method of claim 1 wherein the array of memory cells is arranged in a NAND architecture.
4. The method of claim 1 wherein the adjacent memory cells are in the same column as the first memory cell.
5. The method of claim 1 wherein the adjacent memory cells are in the same row as the first memory cell.
6. The method of claim 1 wherein a soft program operation comprises biasing a control gate of the first memory cell with at least one programming pulse such that a positive programmed voltage is produced on a floating gate of the first memory cell.
7. The method of claim 1 wherein the effect is a coupling between floating gates of adjacent memory cells.
8. A method for programming an array of memory cells arranged in rows and columns in a system having a capacitive coupling effect between adjacent memory cells, each memory cell having a first threshold voltage distribution window and a first programming step voltage that do not take into account the capacitive coupling effect, the method comprising: generating a second programming step voltage that takes into account the capacitive coupling effect, the second programming step voltage greater than the first programming step voltage; and generating a second threshold voltage distribution window that takes into account the capacitive coupling effect, the second threshold voltage distribution window wider than the first threshold voltage distribution window.
9. The method of claim 8 and further including verifying programmed memory cells to an increased threshold voltage that is within the second threshold voltage distribution window.
10. The method of claim 8 wherein the adjacent memory cells are coupled to the same bitline.
11. The method of claim 8 wherein the adjacent memory cells are coupled to the same wordline.
12. The method of claim 8 wherein the first and second threshold voltage distribution windows are positive voltages.
13. The method of claim 8 wherein the array of memory cells is a NAND flash memory array.
14. A method for programming an array of memory cells arranged in rows and columns, the method comprising: generating programming pulses to a first memory cell to program the first memory cell to a first threshold voltage such that a coupling effect from adjacent memory cells is taken into account; verifying that the first memory cell is programmed to the first threshold voltage; generating programming pulses to a second memory cell adjacent the first memory cell; and after generating the programming pulses to the second memory cell, performing a verification operation to determine whether the first memory cell is programmed to a second threshold voltage greater than the first threshold voltage.
15. The method of claim 14 wherein the coupling effect is a capacitive coupling.
16. The method of claim 14 wherein the adjacent memory cells are adjacent on the same bitline.
17. The method of claim 14 wherein the adjacent memory cells are adjacent on the same wordline.
18. The method of claim 14 wherein the array of memory cells are flash memory cells arranged in a NAND architecture.
19. The method of claim 14 wherein a first programming voltage is 100 mV and a subsequent programming voltage is greater than 100 mV.
20. The method of claim 14 wherein a capacitive coupling effect causes an increase in programming voltage for subsequently programmed memory cells.
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April 13, 2006
April 1, 2008
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