Patentable/Patents/US-7354818
US-7354818

Process for high voltage superjunction termination

PublishedApril 8, 2008
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches are formed in the termination region. The trenches of the second plurality of trenches are filled with the dielectric material.

Patent Claims
13 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of manufacturing a semiconductor device having an active region and a termination region surrounding the active region, the method comprising: providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface; forming a first plurality of trenches and a first plurality of mesas in the termination region, each trench of the first plurality of trenches extending from the first main surface toward the heavily doped region to a first depth position; filling the first plurality of trenches in the termination region which is outside and adjacent to the active region with a first dielectric material; forming a second plurality of trenches in the active region and the termination region after forming said first plurality of trenches, each trench of the second plurality of trenches extending from the first main surface toward the heavily doped region to a second depth position; filling the second plurality of trenches with a second dielectric material; planarizing the first main surface; and removing the second dielectric material from the second plurality of trenches in the active region.

2

2. The method according to claim 1 , further comprises: forming columns of the first conductivity type and a second conductivity type in the active region, the second conductivity type being opposite to the first conductivity type, the columns extending from the first main surface toward the heavily doped region to a third depth position.

3

3. The method according to claim 2 , further comprising: implanting at least a portion of a column proximate the first main surface with a dopant of the first conductivity.

4

4. The method according to claim 2 , further comprising: filling the second plurality of trenches in the active region with a third dielectric material.

5

5. The method according to claim 1 , wherein a width of the region defined by the first and second plurality of trenches in the termination region is approximately 20-60 micrometers.

6

6. The method according to claim 1 , wherein at least one of the first and second dielectric material is an oxide.

7

7. The method according to claim 1 , wherein the first dielectric material is identical to the second dielectric material.

8

8. A method of manufacturing a semiconductor device having an active region and a termination region surrounding the active region, the method comprising: providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface; forming a first plurality of trenches and a first plurality of mesas in the termination region, each trench of the first plurality of trenches extending from the first main surface toward the heavily doped region to a first depth position; filling the first plurality of trenches in the termination region which is outside and adjacent to the active region with a first dielectric material; forming a second plurality of trenches in the active region and the termination region after forming the said first plurality of trenches, each trench of the second plurality of trenches extending from the first main surface toward the heavily doped region to a second depth position; filling the second plurality of trenches with a second dielectric material; planarizing the first main surface; removing the second dielectric material from the second plurality of trenches in the active region; and doping at least a portion of a first sidewall of each of the second plurality of trenches in the active region with a dopant of a first conductivity; and doping at least a portion of a second sidewall of each of the second plurality of trenches in the active region with a dopant of a second conductivity type, the second conductivity type being opposite to the first conductivity type.

9

9. The method according to claim 8 , wherein the first dielectric material is identical to the second dielectric material.

10

10. The method according to claim 8 , further comprising: filling the second plurality of trenches in the active region with a third dielectric material.

11

11. The method according to claim 8 , wherein a width of the region defined by the first and second plurality of trenches in the termination region is approximately 20-60 micrometers.

12

12. A method of manufacturing a semiconductor device having an active region and a termination region surrounding the active region, the method comprising: providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface; forming a first plurality of trenches and a first plurality of mesas in the termination region, each trench of the first plurality of trenches extending from the first main surface toward the heavily doped region to a first depth position; filling the first plurality of trenches in the termination region which is outside and adjacent to the active region with a first oxide; forming a second plurality of trenches in the active region and the termination region after forming said first plurality of trenches, each trench of the second plurality of trenches extending from the first main surface toward the heavily doped region to a second depth position; filling the second plurality of trenches with a second oxide; removing the second oxide from the second plurality of trenches in the active region; planarizing the first main surface; forming columns of the first conductivity type and a second conductivity type in the active region, the second conductivity type being opposite to the first conductivity type, the columns extending from the first main surface toward the heavily doped region to a third depth position; and filling the second plurality of trenches in the active region with a third oxide.

13

13. The method according to claim 12 , further comprising: implanting at least a portion of a column proximate the first main surface with a dopant of the first conductivity type.

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Patent Metadata

Filing Date

December 27, 2005

Publication Date

April 8, 2008

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Cite as: Patentable. “Process for high voltage superjunction termination” (US-7354818). https://patentable.app/patents/US-7354818

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