In a data recovery circuit, multiple slicer outputs of incoming data for each data bit, e.g., one or more slicer outputs taken at or near the center of the eye and one or more slicer outputs taken at or near the leading edge and/or trailing edge of the eye, are processed in a manner that reduces the bit-error rate relative to the prior art. The data recovery circuit may be combined with state-of-the-art clock recovery circuits to yield improved clock and data recovery (CDR) circuits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of recovering data from a received data signal, the method comprising: slicing the received data signal substantially at edges of symbol intervals using a first set of one or more slicer thresholds to generate edge samples; slicing the received data signal substantially at centers of the symbol intervals using a second set of one or more slicer thresholds to generate center samples, wherein at least one of the first and second sets has two or more different slicer thresholds; and determining values for data bits in the received data signal based on the edge samples and the center samples.
2. The invention of claim 1 , wherein the first and second sets of slicer thresholds are not identical.
3. The invention of claim 1 , wherein: the edge samples comprise two slicer outputs taken substantially at a prior edge of each symbol interval and two slicer outputs taken substantially at a subsequent edge of each symbol interval; and the center samples comprise three slicer outputs taken substantially at the center of each symbol interval.
4. The invention of claim 3 , wherein, for symbol interval n, the center samples further comprise a slicer output taken substantially at the center of symbol interval n−1 and a slicer output taken substantially at the center of symbol interval n+1.
5. The invention of claim 1 , wherein the values for the data bits are determined using the edge samples and the center samples as inputs to a logic block that implements a mapping of different combinations of edge and center sample values to corresponding data bit values.
6. The invention of claim 5 , wherein different mappings are dynamically selected for use in recovering the data.
7. The invention of claim 1 , wherein each slicing of the received data signal is based on a specified threshold level.
8. The invention of claim 7 , wherein at least one threshold level is dynamically adjusted.
9. The invention of claim 1 , further comprising adjusting at least one of the phase and the frequency of a locally generated clock used to process the received data signal based on the edge samples and the center samples.
10. The invention of claim 1 , wherein the number of slicer thresholds in the first set is different from the number of slicer thresholds in the second set.
11. An apparatus for recovering data from a received data signal, the apparatus comprising: (a) a set of slicers adapted to: (1) slice the received data signal substantially at edges of symbol intervals using a first set of one or more slicer thresholds to generate edge samples; and (2) slice the received data signal substantially at centers of the symbol intervals using a second set of one or more slicer thresholds to generate center samples, wherein at least one of the first and second sets has two or more different slicer thresholds; and (b) a logic block adapted to determine values for data bits in the received data signal based on the edge samples and the center samples.
12. The invention of claim 11 , wherein the first and second sets of slicer thresholds are not identical.
13. The invention of claim 11 , wherein: the edge samples comprise two slicer outputs taken substantially at a prior edge of each symbol interval and two slicer outputs taken substantially at a subsequent edge of each symbol interval; and the center samples comprise three slicer outputs taken substantially at the center of each symbol interval.
14. The invention of claim 13 , wherein, for symbol interval n, the center samples further comprise a slicer output taken substantially at the center of symbol interval n−1 and a slicer output taken substantially at the center of symbol interval n+1.
15. The invention of claim 11 , wherein the values for the data bits are determined using the edge samples and the center samples as inputs to a logic block that implements a mapping of different combinations of edge and center sample values to corresponding data bit values.
16. The invention of claim 15 , wherein different mappings are dynamically selected for use in recovering the data.
17. The invention of claim 11 , wherein each slicer output is based on a specified threshold level.
18. The invention of claim 17 , wherein at least one threshold level is dynamically adjusted.
19. The invention of claim 11 , wherein the slicers comprise: (1) one or more edge slicers, each adapted to slice the received data signal substantially at the prior edge of each symbol interval; and (2) one or more center slicers, each adapted to slice the received data signal substantially at the center of each symbol interval.
20. The invention of claim 19 , wherein the slicers comprise two edge slicers and three center slicers.
21. The invention of claim 11 , wherein at least one of the phase and the frequency of a locally generated clock used to process the received data signal is adjusted based on the edge samples and the center samples.
22. The invention of claim 11 , wherein the number of slicer thresholds in the first set is different from the number of slicer thresholds in the second set.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 18, 2002
April 8, 2008
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