A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A trench isolation type semiconductor device, comprising: a semiconductor substrate defined by an active region and a field region; a trench formed in the field region; an oxide layer conformally formed along the inside of the trench; a liner layer conformally formed along the oxide layer; a field insulating layer formed inside the trench including the oxide layer and the liner layer to substantially a same height as a height of the semiconductor substrate; and a field protection layer formed on the field insulating layer covering all exposed surfaces of the field insulating layer.
2. The trench isolation type semiconductor device of claim 1 , wherein the field protection layer includes a top protection layer and a corner protection layer.
3. The trench isolation type semiconductor device of claim 1 , wherein the field protection layer is a silicon nitride layer.
4. The trench isolation type semiconductor device of claim 1 , wherein the field protection layer has a thickness of 200 to 400 Å.
5. The trench isolation type semiconductor device of claim 1 , wherein the oxide layer is a silicon oxide layer and the liner layer is a silicon nitride layer.
6. The trench isolation type semiconductor device of claim 1 , wherein the field insulating layer is a high density plasma (HDP) silicon oxide layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 13, 2005
April 15, 2008
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