An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said interrupt control system comprising: an interruption message generator for decoding and identifying a message signaled interrupt (MSI) issued by said first peripheral device or said second peripheral device when interruption is to be conducted, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); a stop clock control module coupled to said interruption message generator and said CPU and de-asserting a stop clock signal that is previously asserted to have said CPU enter a power-saving state to have said CPU deactivate said power-saving state in response to said interruption status indicating message; and an interruption status indicating path for transmitting said interruption status indicating message.
2. The interruption control system according to claim 1 wherein said interruption message generator is said north bridge chip.
3. The interruption control system according to claim 1 wherein said stop clock control module is incorporated in said south bridge chip.
4. The interruption control system according to claim 1 wherein said bus bridge chip is a PCI-to-PCI bridge chip.
5. The interruption control system according to claim 1 wherein said interruption status indicating path is an interruption status indicating pin electrically connected between said north bridge chip and said stop clock control module for transmitting said interruption status indicating message from said north bridge chip to said stop clock control module.
6. The interruption control system according to claim 1 wherein said interruption message generator is said north bridge chip, said stop clock control module is incorporated in said south bridge chip, and said interruption status indicating path includes a data bus between said north bridge chip and said south bridge chip.
7. An interruption control system, comprising: a CPU; a south bridge chip comprising a stop clock control module asserting a stop clock signal to said CPU in a power-saving mode and de-asserting said stop clock signal in an interruption mode; a north bridge chip coupled to a bus bridge chip, decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device coupled to said south bridge chip or a second peripheral device coupled to said bus bridge chip, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); and an interruption status indicating path for transmitting said interruption status indicating message from said north bridge chip to said stop clock control module of said south bridge chip to deactivate a power-saving state of said computer system in response to said interruption status indicating message.
8. The interruption control system according to claim 7 wherein said bus bridge chip is a PCI-to-PCI bridge chip.
9. The interruption control system according to claim 7 wherein said first peripheral device is coupled to said south bridge chip via a PCI bus, and said second peripheral device is coupled to said bus bridge chip via another PCI bus.
10. The interruption control system according to claim 7 wherein said interruption status indicating path is an interruption status indicating pin electrically connected between said north bridge chip and said stop clock control module of said south bridge chip.
11. The interruption control system according to claim 7 wherein said interruption status indicating path includes a data bus between said north bridge chip and said south bridge chip.
12. An interruption control method of a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said method comprising steps of: issuing a message signaled interrupt (MSI) from said second peripheral device and transmitting said message signaled interrupt (MSI) to said north bridge chip via said bus bridge chip when an interruption is asserted by said second peripheral device; decoding and identifying said message signaled interrupt (MSI) issued by said second peripheral device, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); and de-asserting a stop clock signal that is previously asserted by said south bridge chip to deactivate a power-saving state of said computer system in response to said interruption status indicating message transmitted to said south bridge chip.
13. The method according to claim 12 further comprising steps of: issuing a message signaled interrupt (MSI) from said first peripheral device and transmitting said message signaled interrupt (MSI) to said north bridge chip via said south bridge chip when an interruption is asserted by said first peripheral device; decoding and identifying said message signaled interrupt (MSI) issued by said first peripheral device, and generating said interruption status indicating message in response to said message signaled interrupt (MSI); and de-asserting said stop clock signal to deactivate said power-saving state of said computer system in response to said interruption status indicating message transmitted to said south bridge chip.
14. The method according to claim 12 wherein said interruption status indicating message is transmitted from said north bridge chip to said south bridge chip via a data bus between said north bridge chip and said south bridge chip.
15. The method according to claim 12 wherein said interruption status indicating message is transmitted from said north bridge chip to said south bridge chip via an interruption status indicating pin electrically connected between said north bridge chip and a stop clock control module of said south bridge chip and said stop clock signal is asserted and de-asserted by said stop clock control module.
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November 30, 2004
April 22, 2008
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