Power supply control circuit and controlling method thereof

1. A power supply control circuit of a semiconductor memory device, comprising: an input/output (I/O) bus voltage generating unit for supplying a power supply voltage to an I/O bus in response to a power supply enable signal; a setting signal generator for outputting a setting signal to set the power supply enable signal in response to a read command signal or a write command signal wherein the setting signal generator is enabled in response to a row active signal; a counting means which is reset in response to the read command signal or the write command signal to count an input clock and then, to output a counting completion signal; and a power supply enable signal generation means enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating the power supply enable signal.

2. The power supply control circuit as recited in claim 1 , further comprising a counter controller for outputting a counter control signal to control the counting means.

3. The power supply control circuit as recited in claim 2 , wherein the counting means is reset to stop a counting operation when the counter control signal is in a first logic level, and the counting means counts the input clock when the counter control signal is in a second logic level.

4. The power supply control circuit as recited in claim 2 , wherein the counter controller includes: a NOR gate receiving the read command signal and the write command signal; and an NAND gate receiving an output signal of the NOR gate and the power supply enable signal to output the counter control signal.

5. The power supply control circuit as recited in claim 1 , wherein the power supply enable signal generation means includes a set-reset (SR) latch to output the power supply enable signal.

6. The power supply control circuit as recited in claim 5 , wherein the power supply enable signal generation means includes: a reset signal generator for outputting a reset signal to reset the power supply enable signal generation means in response to the counting completion signal.

7. The power supply control circuit as recited in claim 6 , wherein the reset signal generator outputs the reset signal activated in synchronization with a rising edge of the counting completion signal.

8. The power supply control circuit as recited in claim 7 , wherein the reset signal generator includes: an inverter receiving the counting completing signal; a delay unit for delaying an output signal of the inverter by a predetermined time; and a NAND gate for performing a logic NAND operation to the counting completing signal and an output signal of the delay unit so as to output the reset signal.

9. The power supply control circuit as recited in claim 6 , wherein the setting signal generator includes: a NOR gate for performing a logic NOR operation to the read command signal and the write command signal; an inverter receiving an output signal of the NOR gate; a NAND gate receiving the row active signal and an output signal of the inverter; and a delay unit for delaying an output signal of the NAND gate by a predetermined time to output the setting signal.

10. The power supply control circuit as recited in claim 1 , wherein the counting means is a variable counter capable of adjusting a counting number of the input clock.

11. The power supply control circuit as recited in claim 10 , wherein the counting means includes: a clock divider for dividing a frequency of the input clock by a predetermined multiple; and an output selector for selecting one among output signals of the clock divider.

12. The power supply control circuit as recited in claim 11 , wherein the clock divider includes N number of divider stages, each of said N number of divider stages being provided with an inverter and a flip-flop so that an output clock divided by 2n is outputted finally, where N is a positive integer.

13. The power supply control circuit as recited in claim 12 , wherein the Nth flip-flop includes a data output terminal for outputting the divided clock, a data input terminal for receiving an inverted output value of the data output terminal, and a clock input terminal for receiving a count clock in case of N being 1 or an output of an N-1th divider stage in case of N being higher than 1.

14. The power supply control circuit as recited in claim 13 , wherein the flip-flop includes: an input latch for latching a data received through the data input terminal; an output latch for latching a data to be outputted through the data output terminal; a first pass gate for connecting the data input terminal to the input latch when the count clock is in a first logic level; and a second pass gate for connecting the output latch to the data output terminal when the count clock is in a second logic level, whereby the input latch is reset to a predetermined logic level depending on the counter control signal.

15. A method for controlling a power supply circuit, comprising: a) receiving a read command or a write command in response to a row active signal; b) performing a counting operation for an input clock after receiving the read command or the write command; c) activating a power supply enable signal after receiving the read command or the write command; d) deactivating the power supply enable signal after finishing the counting operation; and e) supplying a power supply voltage to an input/output (I/O) bus in response to the power supply enable signal.

16. A method for controlling a power supply circuit, comprising: a) receiving a read command in response to a row active signal; b) performing a counting operation for an input clock after receiving the read command; c) activating a power supply enable signal after receiving the read command; d) receiving a write command in response to a row active signal; e) resetting the counting operation and performing the counting operation again; f) deactivating the power supply enable signal after finishing the counting operation for the write command; g) supplying a power supply voltage to an input/output (I/O) bus in response to the power supply enable signal.