The present invention includes an error correction circuit with a data memory, a control circuit, a parity memory, and a recorder. The data memory is configured to receive and store a set of data. The control circuit is configured to receive the set of data and to generate parity bits in response thereto. A parity memory is coupled to the control circuit and configured to receive and hold parity bits. The control circuit is further configured to combine the parity bits from the parity memory with the set of data from the data memory to determine whether an error occurred in the set of data. The recorder is coupled to the control circuit and configured to record an indication of whether an error occurred in the set of data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An error correction circuit comprising: a data memory configured to receive and store a set of data; a control circuit configured to receive the set of data and to generate parity bits in response thereto; a parity memory coupled to the control circuit configured to receive and hold parity bits, wherein the control circuit is further configured to combine the parity bits from the parity memory with the set of data from the data memory to determine whether an error occurred in the set of data; and a recorder coupled to the control circuit and configured to record either an indication of whether an error occurred in the set of data or whether no error occurred in the set of data.
2. The error correction circuit of claim 1 , wherein the control circuit is further configured to correct any error that occurred in the set of data.
3. The error correction circuit of claim 2 , wherein the recorder is a register configured to set a flag each time an error is corrected in the set of data.
4. The error correction circuit of claim 2 , wherein the recorder is a counter configured to count up each time an error is corrected in the set of data.
5. The error correction circuit of claim 1 , wherein the parity bits are generated according to a modified Hamming code.
6. The error correction circuit of claim 1 , wherein the parity bits from the parity memory are combined with the set of data from the data memory according to a modified Hamming code.
7. A system tester comprising: a testing mechanism; a memory chip coupled to the testing mechanism, the memory chip further comprising: a data memory array configured to hold data; a control circuit configured to receive the data and to generate parity bits therefrom; a parity memory configured to hold the parity bits; the control circuit further configured to receive and combine the data from the data memory array and the parity bits from the parity memory to determine whether an error occurred in the data; and a register coupled to the control circuit and configured to store an indication of whether a failure occurred within the data memory, the register accessible via a data bus on the data memory array.
8. The system tester of claim 7 , wherein the testing mechanism is configured to make a test pass on the memory chip such that operability of the data memory array is tested during the test pass.
9. The system tester of claim 8 , wherein the indication of whether a failure occurred within the data memory is stored in the register as a flag during the test pass of the memory chip.
10. The system tester of claim 9 , wherein testing mechanism is configured to read the flag stored in the register during a special test mode.
11. The system tester of claim 10 , wherein the testing mechanism is configured to determine whether any of the data read out of the data memory is corrected data.
12. A memory device comprising: a data memory configured to store data; means configured to receive the data for generating parity bits from the data; a parity memory configured to receive and hold the parity bits; means configured to receive the data and the parity bits for correcting any errors in the data from storing in the data memory; and means for recording whether either any errors in the data from storing the data in the data memory were corrected or whether there were no such corrections.
13. The memory device of claim 12 , further including a tester coupled to the data memory and configured to run a test on the data memory to determine whether it is operable.
14. The memory device of claim 13 , wherein the means for recording whether any errors occurred in the data is a register that can be accessed by the tester to determine whether any errors occurred in the data from storing the data in the data memory.
15. An error detection system comprising: a tester circuit; a data memory configured to receive and to store a set of data; an error correction circuit configured to receive the set of data and to correct errors in the set of data from its storage in the data memory; and a register coupled to the error correction circuit, the register configured to track each time the error correction circuit corrects errors in the set of data, the register being accesible on a data bus of the memory.
16. The error detection system of claim 15 , wherein the error correction circuit generates parity bits based on the received set of data and stores the parity bits in a parity memory.
17. The error detection system of claim 16 , wherein the error correction circuit is configured to correct errors in the set of data by combining the parity bits and the data from the data memory.
18. The error detection system of claim 15 , wherein the tester circuit is configured to test the data memory during a test pass, wherein the register configured to track each time the error correction circuit corrects errors in the set of data during the test pass, and wherein the tester circuit accesses the register during a special test mode.
19. A method for detecting a failure within a memory device, the method comprising: writing a set of data in a data memory; writing the set of data to an error correction circuit configured to receive the set of data; generating parity bits with the error correction circuit using the set of data; storing the parity bits in a parity memory; logically combining the set of data from the data memory and parity bits from the parity memory; and storing an indication of whether either a failure occurred within the set of data written into the data memory or whether no failure occurred whithin the set of data written into the data memory.
20. The method of claim 19 , wherein the logically combining step further includes combining the set of data from the data memory and parity bits from the parity memory according to a modified Hamming code.
21. A method testing a memory chip with on-chip error correction circuit comprising: providing a memory chip; writing a set of data in a data memory of the memory chip; writing the set of data to an error correction circuit on the memory chip; generating parity bits with error correction circuit; logically combining the set of data from the data memory with the parity bits to determine whether an error occurred within the set of data written into the data memory; correcting errors that occurred within the set of data written into the data memory; storing the indication of whether any errors were corrected in a register; and accessing the register via a data bus of the memory chip.
22. The method of claim 21 , further including logically combining the set of data from the data memory with the parity bits using a modified Hamming code.
23. A system tester comprising: a testing mechanism; a memory chip coupled to the testing mechanism, the memory chip further comprising: a data memory array configured to accept and hold data from the testing mechanism; an error correction circuit configured to receive the data and to generate parity bits therefrom; and a parity memory configured to hold the parity bits, testing system not having direct access to the parity memory; wherein the error correction circuit receives and combines the data from the data memory array and the parity bits from the parity memory to determine whether an error occurred in the data or whether no error occurred in the data, and stores an indication of whether a failure occurred within the data memory.
24. The system tester of claim 23 , further including an error correction register configured to set a flag each time a failure occurred within the data memory.
25. An error correction circuit comprising: a data memory configured to receive and store a set of data; a control circuit configured to receive the set of data and to generate parity bits in response thereto; a parity memory coupled to the control circuit configured to receive and hold parity bits, wherein the control circuit is further configured to combine the parity bits from the parity memory with the set of data from the data memory to determine whether an error occurred in the set of data; and a recorder coupled to the control circuit and configured to alternatively record an indication of when no error occurred in the set of data and an indication of when an error did occur in the set of data and was corrected by the control circuit; wherein the recorder is accessible on a data bus.
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May 19, 2005
May 13, 2008
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