Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data retrieval circuit, comprising: an array of memory cells; a pre-fetch unit for storing data that was pre-fetched from the memory cells into a plurality of data buffers including a first plurality of data buffers and a second plurality of data buffers; an output switching unit coupled to the plurality of data buffers, the output switching unit structured to substantially simultaneously output data from at least one of the first plurality of data buffers and at least one of the second plurality of data buffers in response to a control signal; a first node coupled to the output switching unit, the first node connecting output signal lines from the first plurality of data buffers such that the data output from the first plurality of data buffers through the output switching unit is output over a first common output line; a second node coupled to the output switching unit, the second node connecting output signal lines from the second plurality of data buffers such that the data output from the second plurality of data buffers through the output switching unit is output over a second common output line; a data extractor coupled to the first and second common output lines, the data extractor including a plurality of latches structured to temporarily store data outputted from the output switching unit through the first and second node in parallel; and a parallel to serial data converter structured to, upon receiving a clock signal, generate a serial output signal of the data stored in the data extractor.
2. The data retrieval circuit of claim 1 wherein the plurality of latches of the data extractor comprise a first data latch and a second data latch.
3. The data retrieval circuit of claim 2 wherein the first data latch is coupled to a first portion of the plurality of data buffers, and wherein the second data latch is coupled to a second portion of the plurality of data buffers.
4. The data retrieval circuit of claim 3 wherein each of the first data latch and the second data latch is coupled to one-half of the number of data buffers in the plurality of data buffers.
5. The data retrieval circuit of claim 1 , wherein a single clock signal causes the transfer of data from two of the plurality of data buffers to the data extractor, simultaneously.
6. The data retrieval circuit of claim 5 wherein a number of clock signals used to transfer data from the plurality of data buffers to the data extractor equals one-half the number of data buffers in the plurality of data buffers.
7. The data retrieval circuit of claim 1 wherein the parallel to serial data converter comprises a multiplexer.
8. The data retrieval circuit of claim 7 wherein multiplexer comprises: a first switch coupled to a first input terminal and structured to pass a data signal from the first terminal to an output buffer when the first switch receives a first clock signal; a second switch coupled to a second input terminal and structured to pass a data signal from the second terminal to a multiplexer data latch when the second switch receives the first clock signal; and a third switch coupled to the multiplexer data latch and structured to pass a data signal from the multiplexer data latch to the output buffer when the third switch receives a second clock signal.
9. The data retrieval circuit of claim 7 wherein the multiplexer comprises: an even data input coupled to a first input terminal; an odd data input coupled to a second input terminal; first and second pre-read input terminals to receive first and second pre-read signals, respectively; logic circuitry coupled to the even data input, the odd data input, and the first and second pre-read input terminals, the logic circuitry structured to selectively enable the multiplexer based on data states of one or both of the first and second pre-read signals; and an output circuit coupled to the logic circuit for storing an output signal of the multiplexer.
10. A method for retrieving data from an array of memory cells, comprising: prefetching data from a plurality of memory cells; storing the prefetched data into a first set of data latches including a first and second subset of data latches, wherein each of the first and second subset of data latches include a plurality of data latches; outputting, in parallel, data from one of the first subset of data latches to a first node common to the outputs of the first subset of data latches and data from one of the second subset of data latches to a second node common to the outputs of the second subset of data latches; storing, in parallel, the data outputted through the first node and the data outputted through the second node in a second set of data latches; and converting data stored in the second set of latches into serial data.
11. The method of claim 10 wherein converting data stored in the second set of latches comprises: after a first clock signal is received: transmitting one bit of data that was stored in the second set of latches to an output terminal; and storing at least one bit of data that was stored in the second set of latches into a third set of latches; and after a second clock signal is received: transmitting at least one bit of data that was stored in the third set of latches to the output terminal.
12. The method of claim 11 wherein the third set of latches comprises a single latch.
13. The method of claim 11 wherein the first and second clock signals have opposite phase.
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April 11, 2003
May 20, 2008
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