An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An erase voltage generation circuit in a non-volatile semiconductor memory device, comprising: a high voltage generation unit for generating an erase voltage; a voltage level detection unit for detecting the erase voltage and generating a level detection signal, wherein the level detection signal is activated when the erase voltage reaches a target voltage; an execution time checking unit for generating an execution end signal, wherein the execution end signal is activated in response to a lapse of an erase execution time from a time of activation of the level detection signal; and a discharging unit for discharging the erase voltage as a discharge voltage, wherein the high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.
2. The erase voltage generation circuit of claim 1 , wherein the high voltage generation unit comprises: reference clock generating means for generating a reference clock; pumping clock generating means for generating a pumping clock synchronized with the reference clock, the pumping clock generating means being disabled in response to the execution end signal; and high voltage pumping means for pumping the erase voltage in response to the pumping clock.
3. The erase voltage generation circuit of claim 2 , wherein the pumping clock generating means is disabled in response to the activation of the level detection signal.
4. The erase voltage generation circuit of claim 1 , wherein the execution time checking unit comprises: start checking means for generating a start pulse in response to the activation of the level detection signal; counting means for counting the erase execution time from the generation of the start pulse; and end checking means for generating an end pulse according to the lapse of the erase execution time, wherein the end pulse is in response to the transition of an output signal of the counting means.
5. The erase voltage generation circuit of claim 4 , wherein the counting means comprises: an execution counter for generating an output signal that is transited after the erase execution time lapses from the generation of the start pulse; and a recovery counter for generating an output signal that is transited after an erase recovery time lapses from the activating of an execution lapse signal, wherein the execution lapse signal is activated in response to the transition of the output signal of the execution counter.
6. The erase voltage generation circuit of claim 5 , wherein the counting means further comprises: a limit counter for generating an output signal being transited after a limit execution time lapses from the generation of an erase command; and a logic part for generating the execution lapse signal being activated in response to the output signal of the execution counter and the output signal of the limit counter.
7. The erase voltage generation circuit of claim 4 , wherein the start checking means is reset in response to the end pulse.
8. A non-volatile semiconductor memory device, comprising: a memory array including a plurality of non-volatile memory cells; an erase voltage generation circuit operating to apply an erase voltage to the bulk of the non-volatile memory cells that are selected, wherein the erase voltage is discharged as a discharge voltage after an erase execution time lapses from a time when the erase voltage reaches a target voltage; and a control circuit for controlling the erase voltage generation circuit to become enabled in response to an external command.
9. The non-volatile semiconductor memory device of claim 8 , wherein the erase voltage generation circuit comprises: a high voltage generation unit for generating the erase voltage; a voltage level detection unit for detecting the erase voltage and generating a level detection signal, wherein the level detection signal is activated when the erase voltage reaches the target voltage; an execution time checking unit for generating an execution end signal, wherein the execution end signal is activated in response to the lapse of an erase execution time from the activation of the level detection signal; and a discharging unit for discharging the erase voltage as the discharge voltage, wherein the high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.
10. A method of operating an erase voltage generation circuit in a non-volatile semiconductor memory device, comprising the steps of: causing an erase voltage to rise to a target voltage; detecting the erase voltage and generating a level detection signal, wherein the level detection signal is activated when the erase voltage reaches the target voltage; generating an execution end signal, wherein the execution end signal is activated in response to the lapse of an erase execution time from the activation of the level detection signal discharging the erase voltage as a discharge voltage in response to the activation of the execution end signal.
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December 7, 2006
June 3, 2008
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