A data encryption/decryption system comprising a cryptographic interface operatively coupled between a host device and a data storage device is disclosed. The host and data storage devices include respective IDE controllers supporting full ATA protocol. The cryptographic interface includes a host device-side IDE controller and a data storage device-side IDE controller, each controller supporting partial ATA protocol. The cryptographic interface also includes a cipher engine adapted to transparently perform real time data ciphering during IDE/ATA data transfer between the host and data storage devices in conjunction with the host device-side IDE controller and the data storage device-side IDE controller.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data ciphering system comprising: at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, said at least one cryptographic interface adapted to perform data burst initialization procedure with said at least one host device and said at least one data storage device during Ultra Direct Memory Access (UDMA) data transfer; and said at least one cryptographic interface adapted to perform real time data encryption and decryption during said UDMA data transfer between said at least one host device and said at least one data storage device, where said at least one cryptographic interface is configured to process data at least as fast as said at least one host device and said at least one data storage device so as not to impair the overall data transfer efficiency.
2. A data ciphering system comprising: at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, said at least one cryptographic interface adapted to perform data burst initialization procedure with said at least one host device and said at least one data storage device during Ultra Direct Memory Access (UDMA) data transfer; and said at least one cryptographic interface adapted to perform real time data encryption during said UDMA data transfer between said at least one host device and said at least one data storage device, where said at least one cryptographic interface is configured to process data at least as fast as said at least one host device and said at least one data storage device so as not to impair the overall data transfer efficiency.
3. A data ciphering system comprising: at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, said at least one cryptographic interface adapted to perform data burst initialization procedure with said at least one host device and said at least one data storage device during Ultra Direct Memory Access (UDMA) data transfer; and said at least one cryptographic interface adapted to perform real time data decryption during said UDMA data transfer between said at least one host device and said at least one data storage device, where said at least one cryptographic interface is configured to process data at least as fast as said at least one host device and said at least one data storage device so as not to impair the overall data transfer efficiency.
4. A data ciphering system comprising: at least one cryptographic interface operatively coupled between at least one host device and at least one data storage device, said at least one cryptographic interface adapted to perform data burst initialization procedure with said at least one host device and said at least one data storage device during Ultra Direct Memory Access (UDMA) data transfer; and said at least one cryptographic interface adapted to intercept at least one UDMA data transfer between said at least one host device and said at least one data storage device, and transparently performs real time data cipher processing on said at least one intercepted UDMA data transfer, where said at least one cryptographic interface is configured to process data at least as fast as said at least one host device and said at least one data storage device so as not to impair the overall data transfer efficiency.
5. A data ciphering system, comprising: at least one host device; at least one data storage device; and at least one cryptographic interface operatively coupled between said at least one host device and said at least one data storage device, and adapted to intercept and reproduce IDE/ATA dataflow control signals between said at least one host device and said at least one data storage device during Ultra Direct Memory Access (UDMA) data transfer between said at least one host device and said at least one data storage device, wherein said IDE/ATA dataflow control signals during said UDMA data transfer include data burst initialization, data burst pausing, and data burst termination procedures; said at least one cryptographic interface transparently performs real-time data ciphering processing on at least one intercepted UDMA data transfer; and said at least one cryptographic interface is configured to process data at least as fast as the at least one host device and the at least one data storage device so as not to impair the overall data transfer efficiency.
6. A data ciphering system, comprising: at least one host device; at least one data storage device; and at least one cryptographic interface operatively coupled between said at least one host device and said at least one data storage device, and adapted to delay forwarding of IDE/ATA dataflow control signals between said at least one host device and said at least one data storage device during IDE/ATA PIO data transfer between said at least one host device and said at least one data storage device, wherein said IDE/ATA dataflow control signals during the IDE/ATA PIO data transfer include read data strobes and write data strobes; said at least one cryptographic interface transparently performs real-time data ciphering processing on at least one intercepted IDE/ATA data transfer; and said at least one cryptographic interface is configured to process data at least as fast as the at least one host device and the at least one data storage device so as not to impair the overall data transfer efficiency.
7. A data ciphering system, comprising: at least one host device; at least one data storage device; and at least one cryptographic interface operatively coupled between said at least one host device and said at least one data storage device, and adapted to delay forwarding and generate IDE/ATA dataflow control signals between said at least one host device and said at least one data storage device, wherein said IDE/ATA dataflow control signals during PIO data-out transfer includes write data strobes; said at least one cryptographic interface further comprising at least one cipher engine adapted to transparently perform real time cipher data processing during the PIO data-out transfer between said at least one host device and said at least one data storage device; and said at least one cryptographic interface is configured to process data at least as fast as the at least one host device and the at least one data storage device so as not to impair the overall data transfer efficiency.
8. A data ciphering system, comprising: at least one host device; at least one data storage device; and at least one cryptographic interface operatively coupled between said at least one host device and said at least one data storage device, and adapted to generate, forward, and cease forwarding IDE/ATA dataflow control signals between said at least one host device and said at least one data storage device during PIO data-in transfer between said at least one host device and said at least one data storage device, wherein said IDE/ATA dataflow control signals during said PIO data-in transfer include read data strobes; said at least one cryptographic interface further comprising at least one cipher engine adapted to transparently perform real time cipher data processing during the PIO data-in transfer between said at least one host device and said at least one data storage device; and said at least one cryptographic interface is configured to process data at least as fast as the at least one host device and the at least one data storage device so as not to impair the overall data transfer efficiency.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 6, 2003
June 10, 2008
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