Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method

1. A memory cell array driving method for performing a writing operation on a selected memory cell in a memory cell array which includes a plurality of memory cell units arranged longitudinally and transversely in a matrix configuration and control gate lines, the memory cell units each comprising a semiconductor substrate having a high concentration impurity diffusion layer provided as a source diffusion layer in at least a part of a surface thereof, a column-shaped semiconductor layer provided on the semiconductor substrate perpendicularly to the semiconductor substrate and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof, the column-shaped semiconductor layer being electrically isolated from the semiconductor substrate, a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate, a second impurity diffusion layer provided at a lower end of the memory cell arrangement, and a selection transistor connecting the second impurity diffusion layer and the first impurity diffusion layer, the control gates of the memory cells in the memory cell units being connected commonly to the corresponding control gate lines, the driving method comprising the steps of: (s1) applying a positive source voltage to the source diffusion layers of the respective memory cell units; (s2) applying a grounding voltage to a drain diffusion layer of a memory cell unit including the selected memory cell; (s3) applying a writing voltage to a control gate line connected to the selected memory cell; and (s4) applying a writing prevention voltage to drain diffusion layers of memory cell units not including the selected memory cell for prevention of writing to unselected memory cells which share the control gate line connected to the selected memory cell.

2. The memory cell array driving method of claim 1 , wherein a group of the steps s1, s2 and s4 are executed firstly in time-staggered manner or simultaneously, and the step s3 is executed lastly.

3. The memory cell array driving method of claim 1 , wherein the source voltage is not higher than the writing prevention voltage.

4. The memory cell array driving method of claim 1 , wherein the selection transistor has a breakdown voltage not lower than one half the writing prevention voltage, and the source voltage is one half the writing prevention voltage.

5. A memory cell array driving method for performing a writing operation on a selected memory cell in a memory cell array including a plurality of memory cell units arranged longitudinally and transversely in a matrix configuration and control gate lines, the memory cell units each comprising a semiconductor substrate having a high concentration impurity diffusion layer provided as a source diffusion layer in at least a part of a surface thereof, a column-shaped semiconductor layer provided on the semiconductor substrate perpendicularly to the semiconductor substrate with a part of a bottom thereof being in contact with the source diffusion layer, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof, a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate, a second impurity diffusion layer provided at a lower end of the memory cell arrangement, and a selection transistor connecting the second impurity diffusion layer and the first impurity diffusion layer, the control gates of the memory cells in the memory cell units being connected commonly to the corresponding control gate lines, the driving method comprising the steps of: (s1) applying a positive source voltage to the source diffusion layers of the respective memory cell units; (s2) applying a grounding voltage to a drain diffusion layer of a memory cell unit including the selected memory cell; (s3) applying a writing voltage to a control gate line connected to the selected memory cell; and (s4) applying a writing prevention voltage to drain diffusion layers of memory cell units not including the selected memory cell for prevention of writing to unselected memory cells which share the control gate line connected to the selected memory cell.

6. The memory cell array driving method of claim 5 , wherein a group of the steps s1, s2 and s4 are executed firstly in time-staggered manner or simultaneously, and the step s3 is executed lastly.

7. The memory cell array driving method of claim 5 , wherein the source voltage is not higher than the writing prevention voltage.

8. The memory cell array driving method of claim 5 , wherein the selection transistor has a breakdown voltage not lower than one half the writing prevention voltage, and the source voltage is one half the writing prevention voltage.