Method of programming and erasing a p-channel BE-SONOS NAND flash memory

1. A programming method for a p-channel flash memory cell, the memory cell including a gate, a source, a drain, and a channel between the source and the drain, comprising: (a) applying a first voltage to the gate, and (b) applying a second voltage to either the source or the drain, wherein the second voltage is sufficiently greater than the first voltage so as to cause negative Fowler-Nordheim hole injection from the channel, such that the cell is caused to be in a programmed state.

2. A programming method for a memory device, the memory device comprising a NAND array of memory cells, the array comprises one or more word lines and one or more bit lines, each bit line comprises a bit line transistor connected to a string of p-channel memory cells, the string of p-channel memory cells including N series connected memory cells and the N th memory cell connected to a source line transistor, comprising: (a) applying a first voltage to each bit line that corresponds to each selected string of memory cells in the array of memory cells; (b) applying a second voltage to each bit line that corresponds to each unselected string of memory cells, wherein the first voltage is greater than the second voltage; (c) applying a third voltage to each bit line transistor, wherein the second voltage is greater than the third voltage; (d) applying the third voltage to each source line transistor; (e) applying the third voltage to each word line that corresponds to each unselected memory cell; and (f) applying a forth voltage to the word line that corresponds to each selected memory cell, resulting in Fowler-Nordheim hole injection, thereby causing the memory cell to be in a programmed state, wherein the third voltage is greater than the forth voltage.

3. The programming method of claim 2 , wherein each of the second, third and forth voltages are negative voltages with respect to the first voltage.

4. The programming method of claim 2 , wherein the Fowler-Nordheim hole injection in the unselected string of memory cells are insufficient to program the unselected memory cells.

5. The programming method of claim 2 , wherein no Fowler-Nordheim hold injection occurs in a plurality of the unselected memory cells.

6. A programming method for a memory device, the memory device comprising a NAND array of memory cells, the array comprises one or more word lines and one or more bit lines, each bit line comprises a bit line transistor connected to a string of p-channel memory cells, the string of p-channel memory cells including N series connected memory cells and the N th memory cell connected to a source line transistor, comprising: (a) applying a first voltage to each bit line that corresponds to each selected memory cell in the array of memory cells; (b) applying a second voltage to each bit line that corresponds to each unselected memory cell, wherein the first voltage is greater than the second voltage; (c) applying a third voltage to each bit line transistor, wherein the second voltage is greater than the third voltage; (d) applying the first voltage to each source line transistor; (e) applying the second voltage to each word line that corresponds to each unselected memory cell; and (f) applying a forth voltage to the word line that corresponds to each selected memory cell, resulting in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state, wherein the third voltage is greater than the forth voltage.

7. The programming method of claim 6 , wherein each of the second, third and forth voltages are negative voltages with respect to the first voltage.