A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory cell comprising: a wordline; a first digital inverter, the first digital inverter including a first input and a first output, at least the first input having a capacitance; a second digital inverter, the second digital inverter including a second input and a second output, at least the second input having a capacitance; a first feedback connection, the first feedback connection connecting the first output to the second input and comprising a first resistive element; and a second feedback connection, the second feedback connection connecting the second output to the first input and comprising a second resistive element; wherein the memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline, and the first and second resistive elements are configured such that the first and second feedback connections have respective resistance-capacitance induced delays longer than the applied read voltage pulse.
2. The memory cell of claim 1 , wherein the memory cell comprises complementary metal-oxide-semiconductor circuitry.
3. The memory cell of claim 1 , wherein at least one of the first and second digital inverters comprises an n-type field effect transistor and a p-type field effect transistor.
4. The memory cell of claim 1 , wherein the memory cell further comprises: a first bitline; a first access transistor, the first access transistor connecting the first bitline to the first output; a second bitline; and a second access transistor, the second access transistor connecting the second bitline to the second output.
5. The memory cell of claim 4 , wherein the first and second access transistors are operative to be switched on and off by the wordline.
6. The memory cell of claim 4 , wherein at least one of the first and second access transistors comprises an n-type field effect transistor.
7. The memory cell of claim 4 , wherein the first and second bitlines are configured to be charged to a high logic state voltage before reading the memory cell.
8. The memory cell of claim 4 , wherein at least one of the first and second bitlines comprises tungsten, aluminum or copper, or a combination thereof.
9. The memory cell of claim 1 , wherein the memory cell is configured such that writing to the memory cell includes applying a write voltage pulse to the wordline, and the write voltage pulse is longer than the resistance-capacitance induced delays of the first and second feedback connections.
10. The memory cell of claim 1 , wherein at least one of the first and second resistive elements comprises metal nitride, metal oxynitride or metal oxide.
11. The memory cell of claim 1 , wherein at least one of the first and second resistive elements comprises metal silicide.
12. The memory cell of claim 1 , wherein at least one of the first and second resistive elements comprises doped silicon.
13. The memory cell of claim 1 , wherein the wordline comprises polysilicon.
14. An integrated circuit comprising a plurality of memory cells, at least one of the plurality of memory cells comprising: a wordline; a first digital inverter, the first digital inverter including a first input and a first output, at least the first input having a capacitance; a second digital inverter, the second digital inverter including a second input and a second output, at least the second input having a capacitance; a first feedback connection, the first feedback connection connecting the first output to the second input and comprising a first resistive element; and a second feedback connection, the second feedback connection connecting the second output to the first input and comprising a second resistive element; wherein the memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline, and the first and second resistive elements are configured such that the first and second feedback connections have respective resistance-capacitance induced delays longer than the applied read voltage pulse.
15. The integrated circuit of claim 14 , wherein the integrated circuit comprises static random access memory circuitry.
16. The integrated circuit of claim 14 , wherein the at least one of the plurality of memory cells is configured such that writing to the at least one of the plurality of memory cells includes applying a write voltage pulse to the wordline, and the write voltage pulse is longer than the resistance-capacitance induced delays of the first and second feedback connections.
17. The integrated circuit of claim 14 , wherein the at least one of the plurality of memory cells further comprises: a first bitline; a first access transistor, the first access transistor connecting the first bitline to the first output; a second bitline; and a second access transistor, the second access transistor connecting the second bitline to the second output.
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April 24, 2006
July 8, 2008
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