Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in the interface between the device isolation layer and the source/drain region is reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a semiconductor device comprising: forming a device isolation layer in a field region of a semiconductor substrate to define an active region; forming a gate electrode on the active region; forming source/drain regions on opposite sides of the gate electrode; forming a photoresist pattern on the semiconductor substrate that exposes a part of each source/drain region adjacent to the device isolation layer and masks a remaining part of each source/drain region; implanting ions using the photoresist pattern as a mask to form an amorphous layer in the exposed part of each source/drain region adjacent to the device isolation layer; and forming a silicide layer on the surface of the source/drain regions including the amorphous layer.
2. A method as defined in claim 1 , wherein the ions comprise Ge + ions.
3. A method as defined in claim 1 , wherein forming the silicide layer on the surface of the source/drain regions comprises: depositing a refractory metal on the semiconductor substrate; and performing a thermal process to form the silicide layer at an interface between the refractory metal and the at least one of the source region or the drain region.
4. A method as defined in claim 1 , further comprising forming an insulating layer on the gate and the source/drain regions.
5. A method as defined in claim 4 , further comprising forming a contact hole in the insulating layer.
6. A method as defined in claim 5 , further comprising forming a metal line on the insulating layer.
7. A method as defined in claim 1 , wherein forming the device isolation layer comprises: forming an oxidation-resistant insulating layer; and selectively removing parts of the oxidation-resistant insulating layer; and performing a local oxidation process on the exposed silicon.
8. A method as defined in claim 7 , wherein the oxidation-resistant insulating layer comprises a nitride layer.
9. A method as defined in claim 7 , wherein the oxidation-resistant insulating layer comprises an oxide layer and a nitride layer.
10. A method as defined in claim 1 , wherein forming the device isolation layer comprises: forming an oxidation-resistant insulating layer in the active regions; forming a trench by selectively removing the semiconductor substrate in a field region; forming an oxide layer to fill the trenches; and selectively removing the oxide layer by a CMP process to expose the surface of the semiconductor substrate.
11. A method as defined in claim 10 , wherein the oxidation-resistant insulating layer comprises a nitride layer.
12. A method as defined in claim 10 , wherein the oxidation-resistant insulating layer comprises an oxide layer and a nitride layer thereon.
13. A method as defined in claim 1 , wherein the amorphous layer has a thickness of from 1 μm to 5 μm.
14. A method as defined in claim 1 , wherein forming the device isolation layer comprises a LOCOS process or a shallow trench isolation (STI) process.
15. A method as defined in claim 1 , wherein the silicide layer comprises Si x W y or SiTi x .
16. A method as defined in claim 1 , wherein the gate electrode comprises silicon.
17. A method as defined in claim 16 , wherein the silicide layer is also formed on the surface of the gate electrode.
18. A method as defined in claim 1 , wherein forming the photoresist pattern on the semiconductor substrate also masks the device isolation layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 29, 2004
July 15, 2008
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