A film, based on polyimide or epoxy, is laminated onto a surface of a substrate under a vacuum, so that the film closely covers the surface and adheres thereto. Contact surfaces to be formed on the surface are uncovered by opening windows in the film. A contact is established in a plane manner between each uncovered contact surface and a layer of metal. This establishes a large-surface contact providing high current density for power semiconductor chips.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for making contact with at least one electrical contact surface on a surface of a substrate, comprising: laminating under vacuum a film, made of electrically insulating plastic, onto the surface of the substrate the film covering and adhering to the surface of the substrate with a tight fit despite a variation in height as high as 500 μm; forming at least one window in the film to expose each of the at least one electrical contact surface; and making planar contact with each of the at least one electrical contact surface by at least one layer made of electrically conducting material.
2. The method as claimed in claim 1 , wherein the surface of the substrate is populated with at least one semiconductor chip, on each of which is at least one contact surface to which contact is to be made, and wherein said laminating produces the film covering and adhering to each semiconductor chip with a tight fit.
3. The method as claimed in claim 2 , wherein each at least one semiconductor chip is a power semiconductor chip.
4. The method as claimed in claim 3 , wherein the film is made of a plastic based on at least one of a polyimide, polyethylene, polyphenol, polyether ether ketone and epoxy.
5. The method as claimed in claim 4 , wherein the film has a thickness of 25 μm to 150 μm.
6. The method as claimed in claim 5 , further comprising tempering after said laminating of the film.
7. The method as claimed in claim 6 , wherein said laminating is repeated as needed to obtain the thickness of 25 μm to 150 μm.
8. The method as claimed in claim 7 , wherein said forming of the at least one window uses laser ablation.
9. The method as claimed in claim 8 , wherein the film is photosensitive, and wherein said forming of the at least one window uses a photolithographic process.
10. The method as claimed in claim 9 , wherein the at least one layer is a plurality of partial layers made of different electrically conducting material arranged one above another.
11. The method as claimed in claim 10 , further comprising creating at least one conductor track at least one of in and on the layer of electrically conducting material after said making of the planar contact.
12. The method as claimed in claim 11 , further comprising repeating said laminating, forming of the window, making of the planar contact, and creating of the conductor track to fabricate a multi-layer device.
13. A device, comprising: a substrate having a surface on which are arranged electrical contact surfaces, and height differences of the surface being of up to 500 μm; a film of electrically insulating material laminated by vacuum onto the surface, fitting the surface tightly and adhering to the surface despite the height difference as high as 500 μm, said film having windows corresponding to the electrical contact surfaces; and a layer of electrically conducting material in planar contact with the electrical contact surfaces through the windows in said film.
14. The device as claimed in claim 13 , wherein said substrate includes at least one semiconductor chip, each having at least one of the electrical contact surfaces, said film fitting tightly against the at least one semiconductor chip and the at least one of the electrical contact surfaces corresponding to one of the windows in said film through which said layer of electrically conducting material is in planar contact with the at least one of the electrical contact surfaces.
15. The device as claimed in claim 14 , wherein each of the at least one semiconductor chip is a power semiconductor chip.
16. A method for making contact with at least one electrically conducting layer of a plurality of layers, comprising: depositing a plurality of layers directly on an upper surface of an insulating base layer, the layers including at least one electrically conducting layer, and covering partially the insulating base layer and other layers of the plurality of layers; laminating a film covering and adhering tightly to upper surfaces of different layers of the plurality of layers having a variation in height as high as 500 μm, and an exposed portion of the insulating base layer, and preventing planarization; forming at least one window in the film to expose an upper surface of each of the at least one electrically conducting layer; and making a planar contact with the exposed upper surface of each of the at least one electrically conducting layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 25, 2002
July 22, 2008
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